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Auralize: Text to Tune

Auralize: Text to Tune

引用

Emerging Smart computing and Informatics (ESCI), conference on

作者： Swati V Penumarthi Hima Varshini D. Navya Neetu Srivastava Department of Computer Science and Engineering Amrita School of Computing Bengaluru Amrita Vishwa Vidyapeetham India Department of Mathematics Amrita School of Engineering Bengaluru Amrita Vishwa Vidyapeetham India

ISBN: (数字)9798331515683

ISBN: (纸本)9798331515690

The fusion of music and technology has expanded rapidly. AI, machine learning, and signal processing are playing increasingly vital roles in music production, analysis, and generation. This framework introduces a comprehensive framework for automated music processing, including text-to-music generation, genre classification, and noise filtering. This model excels in complex classification tasks, efficiently identifies genre specific features, and achieves a high success rate in genre differentiation. Spectral Subtraction Noise Reduction algorithm refines the audio quality. It ensures that noise is reduced based on its unique characteristics, preserving clarity and maintaining the distinct elements that define various music styles. In conclusion, such an all-integrated system has potential for practical applications in the tasks like music indexing and retrieval or adaptive audio enhancement. Furthermore, this framework provides a basis for further improvements in intelligent music generation and classification.

关键词： Support vector machines Filtering Mood Noise Noise reduction signal processing algorithms Music Production Multiple signal classification Informatics

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A Unified Hardware Accelerator for Fast Fourier Transform and Number Theoretic Transform

A Unified Hardware Accelerator for Fast Fourier Transform an...

引用

international conference on Acoustics, Speech, and signal processing (ICASSP)

作者： Rishabh Shrivastava Chaitanya Prasad Ratnala Durga Manasa Puli Utsav Banerjee Electronic Systems Engineering Indian Institute of Science Bengaluru India

ISBN: (数字)9798350368741

ISBN: (纸本)9798350368758

The Number Theoretic Transform (NTT) is an indispensable tool for computing efficient polynomial multiplications in post-quantum lattice-based cryptography. It has strong resemblance with the Fast Fourier Transform (FFT), which is the most widely used algorithm in digital signal processing. In this work, we demonstrate a unified hardware accelerator supporting both 512-point complex FFT as well as 256-point NTT for the recently standardized NIST post-quantum key encapsulation and digital signature algorithms ML-KEM and MLDSA respectively. Our proposed architecture effectively utilizes the arithmetic circuitry required for complex FFT, and the only additional circuits required are for modular reduction along with modifications in the control logic. Our implementation achieves performance comparable to state-of-the-art ML-KEM / ML-DSA NTT accelerators on FPGA, thus demonstrating how an FFT accelerator can be augmented to support NTT and the unified hardware can be used for both digital signal processing and post-quantum lattice-based cryptography applications.

关键词： Fast Fourier transforms signal processing algorithms Digital signal processing NIST Polynomials Cryptography Logic Speech processing Hardware acceleration Field programmable gate arrays

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Semantic-oriented Visual Prompt Learning for Class Incremental Learning

Semantic-oriented Visual Prompt Learning for Class Increment...

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international conference on Acoustics, Speech, and signal processing (ICASSP)

作者： Shuai Guo Yang Gu Yuan Ma Yingwei Zhang Weining Weng Jun Liu Weiwei Dai Yiqiang Chen Beijing Key Laboratory of Mobile Computing and Pervasive Device Institute of Computing Technology Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China Institute of Digital Ophthalmology and Visual Science Changsha Aier Eye Hospital Changsha China Peng Cheng Laboratory Shenzhen China

ISBN: (数字)9798350368741

ISBN: (纸本)9798350368758

Class-incremental learning (CIL) enables models to continuously learn new classes while addressing catastrophic forgetting. With the introduction of pre-trained models, new tuning paradigms have emerged for CIL. This paper revisits parameter-efficient fine-tuning (PEFT) methods in the context of incremental learning. Prior studies reveal that PEFT methods’ extended parameters do not directly contribute to semantic perception, limiting performance with significant category and domain gaps. To address this, we propose semantic-oriented visual prompt learning (SVPL), which enhances semantic perception and improves task-specific knowledge extraction. SVPL assigns learnable prompts to each class, using a contrastive group alignment to align prompts to task-specific semantic spaces, thus preserving relationships between old and new knowledge. Additionally, hierarchical semantic delivery allows the semantic transformation of prompt groups from shallow to deep layers to facilitate efficient knowledge mining and enable effective learning of new knowledge. Extensive experimental results on five benchmarks demonstrate the superior performance of our methods.

关键词： Visualization Incremental learning Limiting Semantics Benchmark testing Transformers Stability analysis Acoustics Speech processing Tuning

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Efficient signal processing: Harnessing Distributed Arithmetic for High-Speed FFT Operations

Efficient Signal Processing: Harnessing Distributed Arithmet...

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Intelligent and Innovative Technologies in computing, Electrical and Electronics (IITCEE), international conference

作者： M. Bharathi Krithikaa Mohanarangam Yasha Jyothi M Shirur ECE Mohan Babu University (Erstwhile Sree Vidyanikethan Engineering College) Tirupati Andhra Pradesh India Symbiosis Institute of Technology Symbiosis International (Deemed University) Pune India Electronics and Communication Engineering BNM Institute of Technology Bangalore India

ISBN: (数字)9798331515911

ISBN: (纸本)9798331515928

The present article introduces a novel approach to significantly enhance the computational efficiency of modern Digital signal processing (DSP) processors. The algorithm enhances the efficiency of Sum of Products (SOP) operations, which are essential for real-time signal processing applications, by utilizing Distributed Arithmetic (DA) techniques for the Fast Fourier Transform (FFT) and its inverse (Inverse FFT) (IDFT) computations. The present study undertakes an exhaustive quantitative analysis to assess the computational delays of the proposed 2, 4, and 8-point Fast Fourier Transform (FFT) and Inverse Discrete Fourier Transform (IDFT) across various bit representations (4, 8, and 16-bit). For example, when using 4-bit representations, the computational delays for a 2-point Fast Fourier Transform (FFT) are measured to be 13.318ns, 30.629ns for a 4-point FFT, and 27.779ns for an 8-point FFT. Similarly, the delays for the 2-point Fast Fourier Transform (FFT) in an 8-bit representation are 13.727ns, the 4-point FFT in 22.276ns, and the 8-point FFT in 30.592ns. The study further includes the addition of appropriate delays for IDFT operations, which enhances the understanding of the effectiveness of the approach suggested in various scenarios. Furthermore, the research presents and evaluates three distinct categories of transforms, namely 2-point, 4-point, and 8-point FFT and IDFT structures. These structures utilize different quantities of Look-Up Tables (LUTs) for computational purposes. The research showcases the exceptional computing efficiency of the suggested design through detailed quantitative analysis, emphasizing its potential advantages in improving DSP implementations in practical situations.

关键词： Fast Fourier transforms Statistical analysis signal processing algorithms Digital signal processing Real-time systems Delays Table lookup Computational efficiency Velocity measurement Arithmetic

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Efficient Design and Implementation of a 4-Tap FIR Filter Using Braun Multiplier and Ripple Carry Adder (RCA)

Efficient Design and Implementation of a 4-Tap FIR Filter Us...

引用

international Symposium on Advanced computing and Communication (ISACC)

作者： Jesmin Akter Rahimul I. Mazumdar Centre for Sustainable Polymer Indian Institute of Technology Guwahati India Department of Electronics and Electrical Engineering Indian Institute of Technology Guwahati India

ISBN: (数字)9798331523893

ISBN: (纸本)9798331523909

Finite Impulse Response (FIR) filters are essential components in digital signal processing, with their efficiency significantly influenced by the design of multipliers and adders. This work presents a novel Verilog-based implementation of a 4-tap FIR filter, prioritizing area and power optimization. By utilizing Braun multipliers and Ripple Carry Adders (RCAs), the design achieves a considerable reductions in resource utilization and energy consumption, making it ideal for low-power, compact applications. Detailed simulations and validations conducted using the Xilinx Vivado Design Suite 2024.2 demonstrate the accuracy and reliability of the proposed architecture, with results closely aligning with theoretical predictions. These findings underscore the practicality of the novel design for efficient digital signal processing in embedded systems.

关键词： Technological innovation Embedded systems Accuracy Finite impulse response filters Digital signal processing Computer architecture Very large scale integration Resource management Adders Optimization

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Kernel-Based Anomaly Detection Using Generalized Hyperbolic Processes

Kernel-Based Anomaly Detection Using Generalized Hyperbolic ...

引用

international conference on Acoustics, Speech, and signal processing (ICASSP)

作者： Pauline Bourigault Danilo P. Mandic Department of Computing Imperial College London Department of Electronic and Electrical Engineering Imperial College London

ISBN: (数字)9798350368741

ISBN: (纸本)9798350368758

We present a novel approach to anomaly detection by integrating Generalized Hyperbolic (GH) processes into kernel-based methods. The GH distribution, known for its flexibility in modeling skewness, heavy tails, and kurtosis, helps to capture complex patterns in data that deviate from Gaussian assumptions. We propose a GH-based kernel function and utilize it within Kernel Density Estimation (KDE) and One-Class Support Vector Machines (OCSVM) to develop anomaly detection frameworks. Theoretical results confirmed the positive semi-definiteness and consistency of the GH-based kernel, ensuring its suitability for machine learning applications. Empirical evaluation on synthetic and real-world datasets showed that our method improves detection performance in scenarios involving heavy-tailed and asymmetric or imbalanced distributions. https://***/paulinebourigault/GHKernelAnomalyDetect.

关键词： Support vector machines Heavily-tailed distribution Estimation Machine learning signal processing Kurtosis Data models Kernel Speech processing Anomaly detection

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Adapting Large Language Model for Spatio-Temporal Understanding in Next Point-of-Interest Prediction

Adapting Large Language Model for Spatio-Temporal Understand...

引用

international conference on Acoustics, Speech, and signal processing (ICASSP)

作者： Qiuhan Han Atsushi Yoshikawa Masayuki Yamamura School of Computing Tokyo Institute of Technology Tokyo Japan School of Engineering Kanto Gakuin University Kanagawa Japan

ISBN: (数字)9798350368741

ISBN: (纸本)9798350368758

The widespread deployment of Large Language Models (LLMs) across various sectors has underscored their versatility beyond conventional natural language processing applications. Although LLMs are adept at analyzing time series and geospatial data, their capacity to process human spatio-temporal activity data is not yet fully explored. To bridge this research gap, we introduce "LLM-Next," a model engineered to understand spatio-temporal data for predicting a user’s next Point-of-Interest (POI). We developed a specific data processing approach optimized for both temporal and spatial data and fine-tuned the LLM to improve its contextual awareness of human mobility patterns. Comparative experiments on three distinct datasets of human mobility in the real world demonstrate that LLM-Next outperforms existing baseline models in accuracy, thus redefining benchmarks in the domain.

关键词： Accuracy Large language models Time series analysis Predictive models signal processing Data models Spatial databases Speech processing Predictive analytics Standards

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Performance Optimization of FIR Filters Using Approximate Multipliers

Performance Optimization of FIR Filters Using Approximate Mu...

引用

international conference on Wireless Communications, signal processing and Networking (WiSPNET)

作者： Aluvoju Vivek Arun Sekar Rajasekaran MD. Badhesha Dept. of ECE SR University Warangal Telangana India

ISBN: (数字)9798331524227

ISBN: (纸本)9798331524234

Area, Power, and Delay is the fundamental triangular loop on which complete Very Large Scale Integration(VLSI) depends. Achieving a trade-off among these three parameters is a bit challenging. However, approximate computing makes this possible by compromising accuracy at the output, which is acceptable in multimedia applications. Inspired by this, the approximate design of Full Adder, Compressor, and 4x4, 8x8 Vedic Multipliers used in building an FIR low pass filter is proposed to optimize its performance. Those circuit designs are comparatively evaluated with parameters such as area, power, delay, and Power Delay Product in Digital Cadence. Not only the parametric evaluation but also evaluation is done with image addition as an image processing application. Further, the processed image is evaluated with Structural Similarity Index Measure, Peak signal-To-Noise Ratio, Mean Squared Error, and Mean Absolute Error to validate the proposed method. This metrics evaluation is done using Python code.

关键词： Wireless communication Image coding Accuracy PSNR Finite impulse response filters Low-pass filters signal processing Delays Convolutional neural networks Adders

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A High-Performance 64-Bit ALU for AI applications Using Vedic Sutras and Adaptive Accuracy

A High-Performance 64-Bit ALU for AI Applications Using Vedi...

引用

Device Intelligence, computing and Communication Technologies, (DICCT), international conference on

作者： Arunkumar K Pavithra V V. Prithyusha Department of ECE Saveetha Engineering College Chennai India

ISBN: (数字)9798331543358

ISBN: (纸本)9798331543365

The Arithmetic Logic Unit, an important part of a processor, performs arithmetic as well as logic computations. The demand for better performance in processors has resulted in improved computational algorithms and multifunctionality, so all processor cores now reside on a single chip, but this again results in high processing burdens. Consequently, coprocessors have been employed in offloading addition, multiplication, and DSP applications to reduce the burden and impact overall speed significantly. This work introduces a 64-bit ALU implemented based on the Vedic Mathematics using Sutras for high-speed calculations. An accuracy-configurable radix-4 adder is used to dynamically control accuracy. Power gating is implemented here in order to optimize performance and power efficiency. The work has been implemented with Verilog HDL and synthesized in Xilinx ISE. The result includes performance improvements over reduced delays.

关键词： Performance evaluation Accuracy Power demand signal processing algorithms Logic Reliability Hardware design languages Adders Optimization Arithmetic

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Design and Implementation of signal processing for 2D Scanning Radar with Multi-Reflection Detection Using 60 GHz NRD Guide Pulse Radar

Design and Implementation of Signal Processing for 2D Scanni...

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Intelligent Control, computing and Communications (IC3), international conference on

作者： H Pal Thethi N V Uma Reddy R S Sengar Preethi Dashyam T Mounika Tamam Ali Abd Ulabbas Abedi Geetika Sharma Lovely Professional University Phagwara India Department of Artificial Intelligence and Machine Learning New Horizon College of Engineering Bangalore India Department of Electrical & Electronics Engineering GL Bajaj Group of Institutions Mathura Department of Information Technology GRIET Hyderabad Telangana India Department of Computer Science and Engineering MLR Institute of Technology Hyderabad Telangana India Radiology Techniques Department College of Medical Technology The Islamic University Najaf Iraq Department of Electrical Electronics & Communication Engineering Galgotias university Gerater Noida Uttar Pradesh

ISBN: (数字)9798331527495

ISBN: (纸本)9798331527501

The design and implementation of a signal processing system for a two dimensional (2D) electric scanning radar using multi-reflection detection to identify short range object using 60 GHz NRD (Non Radiative Dielectric) guide pulse radar is presented in this research paper. Designed to increase detection accuracy and precision by processing multiple reflections of the transmitted signals in order to recognize objects at short distances, the radar system is the one. The signal processing algorithms are adapted for MPTS handling, and the system takes advantage of the high frequency properties of the 60 GHz NRD guide. Hardware design, simulation results, and performance evaluation regarding the detection accuracy, range resolution, and processing latency, are also discussed. However, applications like autonomous driving, indoor navigation, and industrial automation require short range, high precision radar system, and this approach offers a big advantage.

关键词： Accuracy Radar measurements Radar clutter Radar detection Radar Radar signal processing Real-time systems Reflection High frequency signal resolution

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