The proceedings contain 39 papers. The topics discussed include: an application specific framework for HLS-based FPGA design of articulated robot inverse kinematics;configuration tampering of BRAM-based AES implementa...
ISBN:
(纸本)9781728119687
The proceedings contain 39 papers. The topics discussed include: an application specific framework for HLS-based FPGA design of articulated robot inverse kinematics;configuration tampering of BRAM-based AES implementations on fpgas;evaluating floating-point intensive applications on OpenCL FPGA platforms: a case study on the SimpleMOC kernel;a composable workflow for productive heterogeneous computing on fpgas via whole-program analysis and transformation;a small and adaptive coprocessor for information flow tracking in ARM SoCs;LaKe: the power of in-network computing;using runtime circuit specialization to accelerate simulations of reconfigurable architectures;and exploring FPGA-specific optimizations for irregular OpenCL applications.
The proceedings contain 42 papers. The topics discussed include: Seiba: an FPGA overlay-based approach to rapid application development;reconfigurable real-time video pipelines on SRAM-based fpgas;on the influence of ...
ISBN:
(纸本)9781728119571
The proceedings contain 42 papers. The topics discussed include: Seiba: an FPGA overlay-based approach to rapid application development;reconfigurable real-time video pipelines on SRAM-based fpgas;on the influence of the FPGA compiler optimization options on the success of the horizontal attack;cycle-accurate debugging of multi-clock reconfigurable systems;full hardware implementation of the post-quantum public-key cryptography scheme Round5;iDocChip - a con?gurable hardware architecture for historical document image processing: text line extraction;and efficient utilization of DSPs and BRAMs revisited: new AES-GCM recipes on fpgas.
The proceedings contain 84 papers. The topics discussed include: adaptive multi-client network-on-chip memory;empty resource compaction algorithms for real-time hardware tasks placement on partially reconfigurable FPG...
ISBN:
(纸本)9780769545516
The proceedings contain 84 papers. The topics discussed include: adaptive multi-client network-on-chip memory;empty resource compaction algorithms for real-time hardware tasks placement on partially reconfigurablefpgas subject to fault occurrence;resource efficient arithmetic effects on RBM neural network solution quality using MNIST;deterministic timing-driven parallel placement by simulated annealing using half-box window decomposition;object recognition on a chip: a complete surf-based system on a single FPGA;configuring field-programmable robot arrays;identifying merge-beneficial software kernels for hardware implementation;a reconfigurablecomputing system based on a cache-coherent fabric;characterizing non-ideal impacts of reconfigurable hardware workloads on ring oscillator-based thermometers;an architecture for reconfigurable multi-core explorations;and a PID controller applied to the gain control of a CMOS camera using reconfigurablecomputing.
The proceedings contain 65 papers. The topics discussed include: an efficient and scalable architecture for real-time distortion removal and rectification of live camera images;power-efficient and scalable virtual rou...
ISBN:
(纸本)9781467329217
The proceedings contain 65 papers. The topics discussed include: an efficient and scalable architecture for real-time distortion removal and rectification of live camera images;power-efficient and scalable virtual router architecture on FPGA;a high-performance reconfigurablecomputing architecture using a magnetic configuration memory;static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices;exploring hardware work queue support for lightweight threads in MPSOCs;a lightweight speculative and predicative scheme for hardware execution;optimizing inter-FPGA communication by automatic cannel adaptation;an automated test framework for experimenting with stochastic behavior in reconfigurable logic;multi-FPGA prototyping environment: large benchmark generation and signals routing;and compact Trie forest: scalable architecture for IP lookup on fpgas.
The proceedings contain 76 papers. The topics discussed include: reconfigurable PDA for the visually impaired using fpgas;embedded harmonic control for trajectory planning in large environments;flexible architecture f...
ISBN:
(纸本)9780769534749
The proceedings contain 76 papers. The topics discussed include: reconfigurable PDA for the visually impaired using fpgas;embedded harmonic control for trajectory planning in large environments;flexible architecture for three classes of optical flow extraction algorithms;automatic synthesis of multiprocessor systems from parallel programs under preemptive scheduling;design and implementation of a resource-efficient communication architecture for multiprocessors on fpgas;automatic instruction-set extensions with the linear complexity spiral search;a real-time embedded system for stereo vision preprocessing using an FPGA;finite precision analysis of the 3GPP standard turbo decoder for fixed- point implementation in FPGA devices;parallel processor for 3D recovery from optical flow;and a reconfigurable platform for frequent pattern mining.
The proceedings contain 77 papers. The topics discussed include: a novel high-density single-event upset hardened configurable SRAM applied to FPGA;FPGA implementation of a decimal floating-point accurate scalar produ...
ISBN:
(纸本)9780769539171
The proceedings contain 77 papers. The topics discussed include: a novel high-density single-event upset hardened configurable SRAM applied to FPGA;FPGA implementation of a decimal floating-point accurate scalar product unit with a parallel fixed-point multiplier;prevention of hot spot development on coarse-grained dynamically reconfigurable architectures;floating point hardware for embedded processors in fpgas: design space exploration for performance and area;FPGA implementations of BCD multipliers;matrix multiplication based on scalable macro-pipelined FPGA accelerator architecture;runtime memory allocation in a heterogeneous reconfigurable platform;hotspot mitigation using dynamic partial reconfiguration for improved performance;base-calling in DNA pyrosequencing with reconfigurable Bayesian network;a modular approach to heterogeneous biochemical model simulation on an FPGA;and acceleration of fractal image compression using the hardware-software co-design methodology.
The proceedings contain 28 papers. The topics discussed include: an image comparison circuit design;hardware signal processing unit for one-dimensional variable-length discrete wavelet transform;rapid prototyping of a...
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ISBN:
(纸本)0769524567
The proceedings contain 28 papers. The topics discussed include: an image comparison circuit design;hardware signal processing unit for one-dimensional variable-length discrete wavelet transform;rapid prototyping of a self-timed ALU with fpgas;on the design of two-level reconfigurable architectures;platform for intrinsic evolution of analogue neural networks;design space exploration of coarse-grain reconfigurable DSPs;an FPGA parallel sorting architecture for the burrows wheeler transform;dynamic voting schemes to enhance evolutionary repair in reconfigurable logic devices;FPGA implementation of DSVPWM modulator;on the design of an FPGA-based OFDM modulator for IEEE 802.16-2004;VHDL core for 1024-point radix-4 FFT computation;FPGA implementation of an efficient multiplier over finite fields GF(2m);and hardware/software implementation of a discrete cosine transform algorithm using systemC.
The proceedings contain 49 papers. The topics discussed include: a reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays;a scalable ECC processor implementation for high-spe...
ISBN:
(纸本)9781538637975
The proceedings contain 49 papers. The topics discussed include: a reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays;a scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures;a single-FPGA architecture for detecting heavy hitters in 100 Gbit/s Ethernet links;accelerating low rank matrix completion on FPGA;aging resilient RO PUF with increased reliability in FPGA;adaptive software-augmented hardware reconfiguration with dataflow design automation;an FPGA-in-the-loop approach for HDL motor controller verification;an FPGA-based prototyping framework for networks-on-chip;and an FPGA-based approach for packet deduplication in 100 gigabit-per-second networks.
The proceedings contain 78 papers. The topics discussed include: a minimalistic architecture for reconfigurable WFS-based immersive-audio;an efficient non-blocking data cache for soft processors;runtime task mapping b...
ISBN:
(纸本)9780769543147
The proceedings contain 78 papers. The topics discussed include: a minimalistic architecture for reconfigurable WFS-based immersive-audio;an efficient non-blocking data cache for soft processors;runtime task mapping based on hardware configuration reuse;modeling and formal control of partial dynamic reconfiguration;hardware particle swarm optimization based on the attractive-repulsive scheme for embedded applications;pruning the design space for just-in-time processor customization;applying model-checking to post-silicon-verification: bridging the specification-realization gap;a dynamically reconfigured network platform for high-speed malware collection;placing streaming applications with similarities on dynamically partially reconfigurable architectures;an application example of a run-time reconfigurable embedded system;and cascading deep pipelines to achieve high throughput in numerical reduction operations.
The proceedings contain 75 papers. The topics discussed include: adaptive controller using runtime partial hardware reconfiguration for unmanned aerial vehicles (UAVs);accelerating the construction of BRIEF descriptor...
ISBN:
(纸本)9781467394062
The proceedings contain 75 papers. The topics discussed include: adaptive controller using runtime partial hardware reconfiguration for unmanned aerial vehicles (UAVs);accelerating the construction of BRIEF descriptors using an FPGA-based architecture;a resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms;aging effects on ring-oscillator-based physical unclonable functions on fpgas;achieving energy-efficiency on MPSoCs: performance and power optimizations;accurate in-situ runtime measurement of energy per operation of system-on-chip on FPGA;a universal hardware API for authenticated ciphers;a real-time reconfigurable architecture for face detection;a 297MOPS/0.4mW ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2;analysis of FPGA and software approaches to simulate unconventional computer architectures;and an optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases.
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