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Efficient Algorithm Analysis Of Kidney Images On FPGA

Efficient Algorithm Analysis Of Kidney Images On FPGA

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IEEE Students' conference on Electrical, Electronics and Computer Science (SCEECS)

作者： G.V. Thanuja Ramya S Dept. Electronics and Communication Engineering Manipal Institute of Technology Manipal Academy of Higher Education Manipal Karnataka India

ISBN: (数字)9798331529833

ISBN: (纸本)9798331529840

The field-programmable gate array (FPGA) offers an effective solution to meet the high-performance requirements of real-time digital signal processors. IP cores developed on FPGAs benefit from the programmable logic's flexibility, efficient timing, and adaptability in algorithm modification, coupled with the processing power provided by the embedded processor. Integrating image processing into this sector is an ideal addition, especially in the growing field of edge detection, which is crucial in areas like image pattern recognition, machine learning, and data processing. This paper presents a case study focused on kidney CT scan images for edge detection, utilizing the Sobel and Canny edge detection techniques on the target FPGA device, xc7z020clg484-1. An IP core was designed and generated using VIVADO software, converting image pixels into binary form for pre-processing through these edge detection algorithms. The algorithms were simulated and synthesized on the xc7z020clg484-1 FPGA, with the entire design implemented in Verilog code to create the IP, which connects to the DMA controller throughout the system. This IP core can process multiple CT scan images simultaneously, making it valuable for various biomedical applications. The primary aim of this research is to compare the Sobel and Canny edge detection algorithms to identify the best approach for developing an IP core, evaluated by metrics such as total power consumption, CPU time, execution time, LUT count, and FF usage. The resulting IP core is efficient and conserves resources, making it suitable for other embedded applications.

关键词： Image edge detection Computed tomography Software algorithms signal processing algorithms Computer architecture Table lookup IP networks Logic Field programmable gate arrays Kidney

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Node Selection for Physical Layer Security Using Graph-Based Vertex-Frequency Representation

Node Selection for Physical Layer Security Using Graph-Based...

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international conference on Acoustics, Speech, and signal processing (ICASSP)

作者： Venugopalachary Kotha Vijay Kumar Chakka Shaik Basheeruddin Shah Nazar T. Ali Artifical Intelligence Cluster UPES Uttarakhand India Dept. of Electrical Engineering Shiv Nadar Institution of Eminence India Department of Electrical Engineering Khalifa University Abu Dhabi UAE

ISBN: (数字)9798350368741

ISBN: (纸本)9798350368758

In multi-hop multi-relay cooperative wireless communication systems, node selection for physical layer security (PLS) is an important problem. By defining secrecy capacity based on localized vertex spectrum (LVS), three optimization problems namely i) the best destination for a given eavesdropper, ii) the upper and lower bounds of secrecy capacity for a given destination and iii) the joint optimal destination-eavesdropper pair which maximizes the secrecy capacity are proposed. The performance of the proposed methods have been shown in terms of secrecy outage probability (SOP) by performing simulations and the enhanced PLS is benchmarked with existing literature.

关键词： Wireless communication Lower bound Spread spectrum communication Physical layer security signal processing Probability power system reliability Security Speech processing Optimization

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Low-power High-Speed CNN Accelerator with Matrix Reodering Techniques for Small Footprint Memory Access

Low-Power High-Speed CNN Accelerator with Matrix Reodering T...

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international conference on Artificial Intelligence in Information and communication (ICAIIC)

作者： Hoseong Kim Daejin Park School of Electronics Engineering Kyungpook National University Daegu Korea

ISBN: (数字)9798331507022

ISBN: (纸本)9798331507039

In the evolution of artificial intelligence (AI), large - scale data volumes are needed to best represent the information. This dataset is expressed by a matrix or tensor. When data volumes increase, the operational throughput of data processing increases, exponentially. However, this is not acceptable for computational devices, such as mobile devices, that are expected to low power consumption and high-performance. As the demands for embedded chip devices in AI software have increased, low-power and high-performance modules for AI software are needed to ensure efficient matrix or tensor data processing. Commonly, as performance enhances, power consumption also increases. In this point, a new matrix operation system is essential to ensure high performance and low-power consumption for efficient matrix data processing. In the matrix operation property, large amounts of computational operation can be reduced and sped up through parallelized data processing. In this paper, to determine the advantages of parallelized matrix operation in terms of performance and power consumption, hardware (ALU and memory) module chip equipped with a parallel operation structure and algorithm is designed to reduce data volumes and operational load. By implementing this module by Verilog, with a multicore processor, the processing speed and power consumption are able to compare with the existing sequential processing method of a single-core structure processor [1] [2]. We conducted an experiment to check the operation and performance of a parallelized module chip. The data are stored in memory to compression form through CNN algorithm software, and this is useful in the operation of the matrix arithmetic. This matrix arithmetic operation load is also reduced in support of the CNN algorithm software. The experimental results most likely confirm that the designed quad-core processor embedded CNN algorithm increased its speed to n*log n scale time complexity and that the memory usage rate, m

关键词： power demand Tensors Multicore processing Software algorithms Data processing Throughput Software Artificial intelligence Time complexity Arithmetic

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Generating Avatar Using HamNoSys and SiGML for British Sign Language

Generating Avatar Using HamNoSys and SiGML for British Sign ...

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international conference on signal processing and communication (ICSC)

作者： Harshit Singh Ashish Mishra Rahul Dubey Vipin Tiwari Computer Science and Engineering Jaypee Institute of Information Technology Noida India Computer Science and Engineering Madhav Institute of Technology and Science Gwalior India Computer Science and Engineering Symbiosis Institute of Technology Pune Campus Symbiosis International (Deemed University) Pune India

ISBN: (数字)9798331511890

ISBN: (纸本)9798331511906

In today's digital world online video lectures have become a crucial tool for learning. Yet, these resources aren't available to a big part of the world's population those who are deaf or hard of hearing. This study presents a new system that aims to make these resources available to everyone by turning spoken words from video lectures into sign language gestures. The system uses advanced video processing to change spoken words into text. It then turns this text into British Sign Language (BSL) glosses, which are then written in the Hamburg Notation system (HamNoSys). Using the Signing Gesture Markup Language (SiGML), the system creates a virtual avatar that can show complex sign language gestures. The heart of this research is in combining cutting-edge technologies to offer a deep learning experience that goes beyond hearing limits and tries to make online education for everyone. Early tests of the system show it has the power to close the current gap in education highlighting how important it is to include everyone in the digital age.

关键词： Heart Sign language Translation Avatars Markup languages Education Auditory system signal processing Turning Information age

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On Parameters of Optimal signals with Extended Duration Synthesis Under Limitations on BER Performance

On Parameters of Optimal Signals with Extended Duration Synt...

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Digital signal processing and its Applications (DSPA), international conference on

作者： Ruslan A. Citaishvili Sergey V. Zavjalov Institute of Electronics and Telecommunications Peter the Great St. Petersburg Polytechnic University St. Petersburg Russia

ISBN: (数字)9798331518752

ISBN: (纸本)9798331518769

We propose optimal pulse shapes for faster-than-Nyquist (FTN) single-carrier signaling under the constraint on correlation coefficient which determines inter-symbol interference (ISI) and bit-error rate (BER) performance. The energy, spectral characteristics and PAPR values are obtained for different optimal signal parameters and presented in this paper. The influence of optimal signal parameters (values of correlation coefficient, pulse duration, precision) and model parameters (amplitude limitation, phase and frequency offset) on spectral and energy efficiency of communication system, is investigated, and efficient values of optimal signal parameters, also as acceptable model parameters, are obtained.

关键词： Correlation coefficient Energy loss Satellites Shape communication systems Spectral efficiency Phase modulation Peak to average power ratio Interference Energy efficiency

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Optimized Low-power FIR Filter Design Using Residue Number system for Energy-Efficient DSP Applications

Optimized Low-Power FIR Filter Design Using Residue Number S...

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international conference on Inventive Computation Technologies (ICICT)

作者： Cheruku Navaneeth Kumar Goud Ch. Kavya S. Bharath JVR Ravindra Dept of Electronics and Communication Engineering Center for Advanced Computing Research Laboratory (C-ACRL) Vardhaman College of Engineering Hyderabad India

ISBN: (数字)9798331512248

ISBN: (纸本)9798331512255

In modern digital signal processing (DSP) systems, power efficiency is a critical design consideration, especially for portable and battery-powered devices. This project presents an optimized low-power FIR (Finite Impulse Response) filter design using the Residue Number system (RNS) to achieve energy-efficient DSP applications. Traditional FIR filters, while effective, are often power-intensive due to the high computational complexity involved. The RNS offers a promising alternative by enabling parallelism and reducing the size of arithmetic operations, leading to lower power consumption without sacrificing performance. In this project, we explore the integration of RNS with FIR filter architecture, focusing on optimizing modular arithmetic operations to reduce power consumption while maintaining high throughput and precision. The design methodology includes theoretical analysis, hardware implementation, and performance evaluation, demonstrating the advantages of using RNS in reducing both dynamic and static power in DSP systems. Experimental results showcase significant power savings compared to conventional FIR filter designs, making this approach highly suitable for next-generation DSP applications in mobile, wireless communication, and IoT devices.

关键词： Performance evaluation Wireless communication power demand Finite impulse response filters Digital signal processing Throughput Energy efficiency Real-time systems Delays Arithmetic

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Research of the Possibilities of Upgrading the Radio Path of a Repeater Using Software-Defined Devices

Research of the Possibilities of Upgrading the Radio Path of...

引用

international Youth conference on Radio Electronics, Electrical and power Engineering (REEPE)

作者： Yury S. Rusov Pavel P. Kurenkov Radioelectronic Systems and Devices Department Bauman Moscow State Technical University Moscow Russian Federation

ISBN: (数字)9798331531836

ISBN: (纸本)9798331531843

This paper analyzes the possibilities of upgrading the onboard repeater of the satellite communication system taking into account the development trend of modern technologies. The objective of the study is to identify a universal technical solution that facilitates the creation of such systems through the utilisation of software-defined radio. The paper's central theme is an in-depth study of the repeater radio channel scheme, with a particular focus on the replacement of a portion of the microwave devices with software-defined radio technology. The study proposes a radio channel model that facilitates a qualitative assessment modernization schemes and the configuration of the software-defined radio program, with the potential to markedly accelerate the development of novel hardware solutions.

关键词： Space vehicles Performance evaluation signal processing algorithms Microwave devices Microwave communication signal processing Repeaters Software Satellite communications Software radio

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Performance Analysis of communication Protocols (I2C, SPI) for embedded Applications with IMU Sensor using Verilog

Performance Analysis of Communication Protocols (I2C, SPI) f...

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Trends in Material Science and Inventive Materials (ICTMIM), international conference on

作者： V.Muneeswaran K.Naresh Kumar P.Manikandan M.Naveen Kumar C.Vishnu Chaithanya M. Ganga Priyadarshini Department of ECE Kalasalingam Academy of Research and Education Tamilnadu India EDA Software Developer Pico2Femto Semiconductor Pvt. Ltd Trichy TamilNadu India

ISBN: (数字)9798331501488

ISBN: (纸本)9798331501495

Effective communication protocols are to be ensured in crucial embedded application that helps for timely data transfer in connected environments, impacting efficiency, energy use, and resource management together with parallel processing of data. Among the available protocols Inter-Integrated Circuit (I2C) and Serial Peripheral Interface (SPI) are widely used due to their distinct features for various applications and their simplicity in data transfer scheme. In this work we aim to assess I2C and SPI performance in embedded application particularly a fall detection system using Verilog HDL, focusing on data transfer rate, power consumption, latency, and hardware complexity. It is evident from the study that I2C's two-wire interface and its capacity of multi-device support make it suitable for power-sensitive applications, though it operates at lower speeds. In contrast, SPI provides high-speed, full-duplex communication but requires more GPIO pins, limiting scalability in implementation. The study offers a comparative analysis through Verilog simulations, with the help of Xilinx Hardware that helps firmware designers to choose the best protocol for their embedded applications. Results obtained emphasize the trade-offs between speed, energy efficiency, and hardware complexity, aiding in the optimization of embedded system designs.

关键词： Protocols embedded systems power demand Data transfer Hardware Energy efficiency Complexity theory Pins Hardware design languages Optimization

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Transfer Learning with Transformer and LSTM for Digital Pre-distortion of Terahertz/mmWave Transceiver

Transfer Learning with Transformer and LSTM for Digital Pre-...

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international conference on Acoustics, Speech, and signal processing (ICASSP)

作者： Gouheng Zhao Kai Ying Qingsong Wen Junwen Zhang Lin Gui School of Electronic Information and Electrical Engineering Shanghai Jiao Tong University Shanghai China Squirrel Ai Learning Bellevue USA Department of Communication Science and Engineering Fudan University Shanghai China

ISBN: (数字)9798350368741

ISBN: (纸本)9798350368758

To ensure high-quality communication, it’s of great value to use digital pre-distortion (DPD) to linearize the core component power amplifier (PA) of terahertz/mmWave transceiver. In this work, we propose transfer learning with Transformer and LSTM for DPD of terahertz/mmWave transceiver, which uses Transformer based PA behavioral model to train effective and lightweight LSTM model for DPD. To collect and analyze the signal data of terahertz/mmWave transceiver, we set up a physical platform for the D-band system. Through experiments, we show that the proposed method is capable of significantly reducing in-band and out-band distortion while avoiding the excessive complexity of DPD models.

关键词： Acoustic distortion Transfer learning power amplifiers Bandwidth Transformer cores Transformers Transceivers Complexity theory Speech processing Long short term memory

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RIS-Enabled Self-Interference Elimination in Monostatic Full-Duplex DFRC systems

RIS-Enabled Self-Interference Elimination in Monostatic Full...

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international conference on Acoustics, Speech, and signal processing (ICASSP)

作者： Linlong Wu Zichao Xiao Bhavani Shankar M. R. Björn Ottersten Interdisciplinary Centre for Security Reliability and Trust University of Luxembourg Luxembourg

ISBN: (数字)9798350368741

ISBN: (纸本)9798350368758

A key challenge in Integrated Sensing and communications (ISAC), especially in Full-Duplex (FD) Dual-Functional Radar-communication (DFRC) systems, is self-interference (SI) caused by signal leakage from the transmitter to the receiver, impairing sensing tasks. Reconfigurable Intelligent Surface (RIS) can manipulate signal reflections with minimal power, making them promising for enhancing 6G communication, yet its potential for SI mitigation in DFRC systems is underexplored. This paper proposes a novel RIS-enabled approach for SI elimination in mono-static full-duplex DFRC systems. Our method decomposes the RIS function into spatial beam-forming and temporal modulation to ensure sufficient target illumination and orthogonality between reflected and transmitted waveforms, effectively eliminating SI without the need for SI channel information. Simulations confirm the effectiveness of the proposed approach in SI elimination and sensing performance.

关键词： Interference cancellation Transmitters Modulation signal processing algorithms Full-duplex system Reconfigurable intelligent surfaces Integrated sensing and communication Reflection Speech processing Surface treatment

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