The proceedings contain 606 papers. The topics discussed include: new industrialization and integratedcircuits industry in the mainland of China;directions for silicon technology as we approach the end of CMOS scalin...
ISBN:
(纸本)9781424457984
The proceedings contain 606 papers. The topics discussed include: new industrialization and integratedcircuits industry in the mainland of China;directions for silicon technology as we approach the end of CMOS scaling;self-powered nanosystem: from nanogenerators to piezotronics;technologies for embedded processors and applications for intelligent control;system architecture, design/circuit and technology optimization for advanced mobile wireless devices;challenge and opportunity in circuit simulation and verification;mobility enhancement in silicon nanowire transistors;wafer-level magnetotransport measurement of advanced transistors - making a powerful technique even more powerful;future of nanoelectronics at the end of the roadmap and beyond;silicon photonics technologies for monolithic electronic-photonic integratedcircuit applications;and source/drain and gate engineering on Si nanowire transistors with reduced parasitic resistance and strained silicon channel.
The proceedings contain 349 papers. The topics discussed include: circuit, MOSFET, and front end process integration trends and challenges for the 180 nm and below: an internationaltechnology roadmap for semiconducto...
ISBN:
(纸本)0780365208
The proceedings contain 349 papers. The topics discussed include: circuit, MOSFET, and front end process integration trends and challenges for the 180 nm and below: an internationaltechnology roadmap for semiconductors perspective;ULSI technologies for system-on-chip (SOC) for the next 10 years;the potential and realization of multi-layers three-dimensional integratedcircuit;challenges in sub 4.13 pm front-end-of-line process;3D integratedcircuit using large grain polysilicon film;high performance logic technology - scaling trend and future challenges;high performance 70 nm CMOS device and key technologies;the semiconductor foundry business and technology trend;methodology of parameter and coupling ratio extraction for source side injection (SSI) flash cell;new global insight in ultra-thin oxide reliability using accurate experimental methodology and theoretical modeling;ultra shallow secondary ion mass spectrometry;and modeling study of scanning capacitance microscopy measurement for P-N junction dopant profile extraction.
The proceedings contain 349 papers. The topics discussed include: circuit, MOSFET, and front end process integration trends and challenges for the 180 nm and below: an internationaltechnology roadmap for semiconducto...
ISBN:
(纸本)0780365208
The proceedings contain 349 papers. The topics discussed include: circuit, MOSFET, and front end process integration trends and challenges for the 180 nm and below: an internationaltechnology roadmap for semiconductors perspective;ULSI technologies for system-on-chip (SOC) for the next 10 years;the potential and realization of multi-layers three-dimensional integratedcircuit;challenges in sub 4.13 pm front-end-of-line process;3D integratedcircuit using large grain polysilicon film;high performance logic technology - scaling trend and future challenges;high performance 70 nm CMOS device and key technologies;the semiconductor foundry business and technology trend;methodology of parameter and coupling ratio extraction for source side injection (SSI) flash cell;new global insight in ultra-thin oxide reliability using accurate experimental methodology and theoretical modeling;ultra shallow secondary ion mass spectrometry;and modeling study of scanning capacitance microscopy measurement for P-N junction dopant profile extraction.
The proceedings contain 472 papers. The topics discussed include: an optimization algorithm for pre-bond TSV probing tests and fault localization;a prebond TSV test scheme using oscillator;improved crystallinity of ul...
ISBN:
(纸本)9781467397179
The proceedings contain 472 papers. The topics discussed include: an optimization algorithm for pre-bond TSV probing tests and fault localization;a prebond TSV test scheme using oscillator;improved crystallinity of ultra-thin amorphous film by 2D-limited regrowth: process and characterization;wafer level chip scale packing for Si-based driver application;Si-based horizontal InAs nanowire transistors;study on neutron radiation effect of FinFET SRAM;research of transient radiation effects on FinFET SRAMs compared with planar SRAMs;AND investigation of the reverse voltage stress on the fluorine plasma treated AlGaN/GaN schottky barrier diodes.
The proceedings contain 426 papers. The topics discussed include: research on design and test method of high performance 6 input LUT;performance enhancement by gate tunable strain in p-type piezoelectric FinFETs;a low...
ISBN:
(纸本)9781538644409
The proceedings contain 426 papers. The topics discussed include: research on design and test method of high performance 6 input LUT;performance enhancement by gate tunable strain in p-type piezoelectric FinFETs;a low power and wideband 28-41GHz PLL design for mm-wave applications;method for practical use of parasitic capacitances of reference current sources in dual-input-stages for increasing the SR of operational amplifiers in inverting connection circuits;studies on ReRAM conduction mechanism and the varying-bias read scheme for MLC and wide temperature range TMO ReRAM;TCAD based design technology co-optimization in advanced CMOS technology;impact of process imperfection of CNFET on circuit-level performance and proposal to improve using approximate circuits;and implementing RISCV system-on-chip for acceleration of convolution operation and activation function based on FPGA.
The proceedings contain 536 papers. The topics discussed include: evolving challenges and techniques for nanometer SoC clock network synthesis;a security coprocessor embedded system-on-chip architecture for smart mete...
ISBN:
(纸本)9781479932962
The proceedings contain 536 papers. The topics discussed include: evolving challenges and techniques for nanometer SoC clock network synthesis;a security coprocessor embedded system-on-chip architecture for smart metering, control and communication in power grid;the threshold voltages of low temperature polycrystalline silicon thin film transistors;toward 0.1V operation of mosfets for ultra-low power applications;GaN-based metal-oxide-semiconductor field-effect transistors;realization of GaN-based mGH frequency planar schottky barrier diodes through air-bridge technology;silicon-migration technology for mems-cmos monolithic integration;design challenges of high speed ADC in CMOS technology for next generation optical communication applications;and 10 years of transistor innovations in system-on-chip (SoC) era.
The proceedings contain 281 papers. The topics discussed include: an integrated SoC for image processing in space flight instruments;performance enhancement of ATZO TFTs by component control and post treatment;a novel...
ISBN:
(纸本)9781728162355
The proceedings contain 281 papers. The topics discussed include: an integrated SoC for image processing in space flight instruments;performance enhancement of ATZO TFTs by component control and post treatment;a novel HSPICE model for dual-threshold independent-gate TFET;impacts of lateral charge migration on data retention and read disturb in 3D charge-trap NAND flash memory;a simple and efficient fuse-trimming circuit for analog design;a two-ASIC front-end for MEMS accelerometers;an ultra-low-voltage single-phase adaptive pulse latch with redundant toggling elimination;MF-Conv: a novel convolutional approach using bit-resolution-based weight decomposition to eliminate multiplications for CNN acceleration;a wafer map defect pattern classification model based on deep convolutional neural network;and a lightweight CNN for low-complexity HEVC intra encoder.
The proceedings contain 651 papers. The topics discussed include: the future of CMOS scaling - parasitics engineering and device footprint scaling;silicon nanowire CMOSFETs: fabrication, characteristics, and memory ap...
ISBN:
(纸本)9781424421855
The proceedings contain 651 papers. The topics discussed include: the future of CMOS scaling - parasitics engineering and device footprint scaling;silicon nanowire CMOSFETs: fabrication, characteristics, and memory application;low dissipation nanoscale transistor physics and operations;status and trends in nanoscale Si-based devices and materials;road-blocks to tera-level nanoelectronics;CMOS gate height scaling;extraction of voltage transfer characteristic of inverter based on TSNWFETs;air spacer MOSFET technology for 20nm node and beyond;scaling study of nanowire and multi-gate MOSFETs;the impact of substrate bias on RTS and flicker noise in MOSFETs operating under switched gate bias;the state-of-the-art mobility enhancing schemes for high-performance logic CMOS technologies;scaling of strain-induced mobility enhancements in advanced CMOS technology;and stress engineering in (100) and (110) nMOSFETs.
The proceedings contain 656 papers. The topics discussed include: CMOSFET scaling through the end of the roadmap;critical technology issues for deca-nanometer MOSFETs;a review of the SOI four-gate transistor;planar an...
详细信息
ISBN:
(纸本)1424401615
The proceedings contain 656 papers. The topics discussed include: CMOSFET scaling through the end of the roadmap;critical technology issues for deca-nanometer MOSFETs;a review of the SOI four-gate transistor;planar and multiple-gate transistors with silicon-carbon source/drain;novel MOSFET devices for RF circuits;CMOS devices architectures for the end of the roadmap and beyond;manufacturing considerations of lithography independent nano-MOS-transistors in the sub-25 nm-region;temperature impact on the Lorentzian noise induced by electron valence band tunneling in partially depleted SOI nMOSFETs;an investigations of the effects of Si thickness-induced variation of the electrical characteristics in FDSOI with block oxide;impact of improved mobility and low flicker noise MOS transistors using accumulation mode fully depleted silicon-on-insulator devices;and characterization of the self-aligned pseudo-SOI devices structures.
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