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检索条件"任意字段=International Microsystems Packaging Assembly and Circuits Technology Conference IMPACT"

共 976 条记录，以下是91-100 订阅

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Breakthroughs in chip embedding technologies leading to the emergence of further miniaturised system-in-packages

Breakthroughs in chip embedding technologies leading to the ...

引用

4th international microsystems, packaging, assembly and circuits technology conference

作者： Manessis, Dionysios Boettcher, Lars Ostmann, Andreas Karaszkiewicz, Stefan Reichl, Herbert Tech Univ Berlin Microperipher Res Ctr D-1000 Berlin Germany Fraunhofer Inst Reliabil & Microintegrat D-13355 Berlin Germany

ISBN: (纸本)9781424443413

Embedding of semiconductor chips into organic substrates allows a very high degree of miniaturization by stacking multiple layers of embedded thin components. This paper shows the realisation of embedded chip QFN-packages (Quad Flat No-Lead) with a size of 10mmx 10mm which were manufactured at prototype level at 10"x14" panels. The embedded chip in the package has a pad pitch of 100 mu m and the resultant QFN package has a total number of 841/Os at 400 mu m footprint pitch. State-of-the-art developments in semi-additive processes by employment of laser-direct-imaging technology (LDI) have demonstrated very fine 18 mu m lines with 10 mu m space between them for the final package copper routing. The work in this paper provides evidence for chip embedding capability at very fine chip pad pitch of 100 mu m and discusses the technology limits. The present work at research prototype level frames the main activities in the EU-Hermes project towards the industrialisation of chip embedding technologies.

关键词： 3D packaging embedded chips Chip in Polymer System in Package PCB technology

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Improving Throughput of Zero-Kerf Singulation for Ultra-Thin Wafers using Stealth Dicing 13

Improving Throughput of Zero-Kerf Singulation for Ultra-Thin...

引用

13th international microsystems, packaging, assembly and circuits technology conference (impact)

作者： Suzuki, Natsuki Atsumi, Kazuhiro Uchiyama, Naoki Ohba, Takayuki Tokyo Inst Technol WOW Alliance Midori Ku 4259 Nagatsuda Yokohama Kanagawa 2268503 Japan Hamamatsu Photon KK 314-5 Shimo Kanzo Iwata Shizuoka 4380193 Japan Grad Sch Creat New Photon Ind Nishi Ku 1955-1 Kurematsu Cho Hamamatsu Shizuoka 4311202 Japan

ISBN: (纸本)9781538656150

This paper describes a technique for improving the throughput in singulation of ultra-thin wafers using a dicing method called Stealth Dicing. We evaluated how beam shaping with a spatial light modulator and the processing laser wavelengths (1080 nm and 1099 nm) having different transmittances in silicon wafers affected the processing performance. By applying Stealth Dicing with aberration correction and multi-beam irradiation using a 1099 nm laser, the throughput was improved by approximately a factor of two compared with conventional Blade Dicing. The method shows promise for achieving high productivity for volume production.

关键词： 3D packaging laser, and aberration correction multi beam spatial light modulator die strength

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300-mm Wafer 3D Integration technology using Hybrid Wafer Bonding

300-mm Wafer 3D Integration Technology using Hybrid Wafer Bo...

引用

8th international microsystems, packaging, assembly and circuits technology conference (impact)

作者： Hozawa, Kazuyuki Aoki, Mayu Hanaoka, Yuko Takeda, Kenichi Hitachi Ltd Cent Res Lab Kokubunji Tokyo 1858601 Japan

ISBN: (纸本)9781479906673

We have developed a low-cost wafer-level three-dimensional (3D) integration technology compatible with 300-mm wafers by using hybrid wafer bonding. This technology includes wafer-to-wafer (W2W) stacking technology with a copper/polymer hybrid wafer bonding and through-silicon via (TSV) reveal process. Bonding of a copper/polymer hybrid wafer achieved good copper-to-copper bonding as well as good polymer-to-polymer bonding without producing any large bonding voids. The misalignment between 300-mm bonding wafers was less than 0.57 mu m. Via-middle TSVs (8 mu m in diameter and 25 mu m in length) were revealed by back grinding (BG) and chemical mechanical polishing (CMP). The electrical connectivity of a three-stacked wafer fabricated by hybrid wafer bonding was confirmed. These results indicate the effectiveness of the proposed 3D integration technology.

关键词： bonding processes chemical mechanical polishing copper electric connectors three-dimensional integrated circuits wafer bonding wafer level packaging

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Development of consistent interconversions between linear viscoelastic functions for multiaxial viscoelastic models 12

Development of consistent interconversions between linear vi...

引用

12th international microsystems, packaging, assembly and circuits technology conference (impact)

作者： Chen, Dao-Long Chiu, Tz-Cheng Lee, Shu-Hua Sung, Po-Hsien Shih, Meng-Kai Tarng, David Hung, Chih-Pin Adv Semicond Engn Inc Grp R&D Kaohsiung Taiwan Natl Cheng Kung Univ Dept Mech Engn Tainan Taiwan

ISBN: (纸本)9781538647196

Characterizations for the comprehensive viscoelastic behaviors of materials were conducted in this research. For considering the multiaxial viscoelastic behaviors of the polymeric constituents in finite element models for package stress and deformation simulations, it is required to construct the mathematical models of the viscoelastic bulk and shear relaxation moduli. In order to obtain the consistent viscoelastic functions, the interconversion relations were developed and applied as a new fitting procedure. By using the consistently fitted values of viscoelastic bulk and shear relaxation moduli, the constitutive behaviors of organic packaging materials by using time-dependent viscoelastic models for warpage predictions could be more accurate.

关键词： Fitting Mathematical model packaging Electromagnetic compatibility Integrated circuit modeling Deformable models Predictive models

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A Novel Through-Hole Filling technology for Next Generation Organic Interposer Applications

A Novel Through-Hole Filling Technology for Next Generation ...

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8th international microsystems, packaging, assembly and circuits technology conference (impact)

作者： Liu, Tao-Chi Wang, Shing-Ru Corey, Michael Enthone Inc Global Dev Applicat Ctr Tao Yuan Taiwan

ISBN: (纸本)9781479906673

We report an approach to full fill the laser drilled through-hole by DC electroplating. A hydrodynamics-sensitive organic compound with selective inhibition being used to Cu electrodeposition is required as an additive of plating bath. Void-free Cu column can be fabricated as the interconnects in the organic substrate of 2.5D IC interposer. The residual dimples were almost eliminated with thin overburden at low current density and high agitation speed. The following Cu thickness thinning by Chemical Mechanical polish (CMP) can be reduced further. 3D X-ray inspection indicates that the filled through-hole of aspect ratio of 2 to 2.5 can be completely filled within 75 minutes, which is the highest speed among the reported interposer metallization. It is also compatible with most of PCB plating equipment. Compare with recent TSV process using semiconductor tool, this novel technology is beneficial to reduce the cost and process of manufacturing. Through-hole filling will have potential applications in 3D IC packaging.

关键词： chemical mechanical polishing copper electroplating filling integrated circuit packaging laser beam machining metallisation three-dimensional integrated circuits

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An Innovative Annealing-Twinned Ag-Au-Pd Bonding Wire for IC and LED packaging

An Innovative Annealing-Twinned Ag-Au-Pd Bonding Wire for IC...

引用

7th international microsystems, packaging, assembly and circuits technology conference (impact)

作者： Tsai, Hsing-Hua Lee, Jun-Der Tsai, Chih-Hsin Wang, Hsi-Ching Chang, Che-Cheng Chuang, Tung-Han Wire Technol Co LTD Taichung 432 Taiwan Natl Taiwan Univ Inst Mat Sci & Engn Taipei 106 Taiwan

ISBN: (纸本)9781467316385;9781467316354

An innovative annealing twinned Ag-(8-30%) Au-(0.01-6%)Pd wire for IC and LED packaging has been developed. It exhibits high thermal stability during aging at 600 degrees C and a small heat affected zone after wire bonding. The mean failure time of this annealing twinned Ag-Au-Pd wire when stressed with a current density of 1.23 x 10(5)A/cm(2) is about double that of the conventional grained Ag-alloy wire. For packaging on Si chips with Al pads, it possesses sufficient intermetallic compounds at the initial as-bonded stage but a slow growth rate during further reliability tests. The excellent reliability of this new bonding wire has been verified in a DDRII BGA IC package and a 0605 LED package. In the LED package, this Ag-alloy wire provides the extra benefit of increasing the light output power (LOP) by about 3.2%.

关键词： Annealing twinned structure Ag-Au-Pd alloy wire Reliability

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Bumping technology and chip & package interaction

Bumping technology and chip & package interaction

引用

2010 5th international microsystems, packaging, assembly and circuits technology conference, impact 2010 and international 3D IC conference

作者： Tsukada, Yutaka Ritsumeikan University Osaka University Japan

Presents a collection of slides covering the following topics: bumping technology; chip-package interaction; and flip chip packaging.

ISBN: (纸本)9781424497836

Presents a collection of slides covering the following topics: bumping technology; chip-package interaction; and flip chip packaging.

关键词： bumping technology chip-package interaction flip chip packaging flip-chip devices packaging

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SiP assembly and Application using Glass Substrate with Through Vias 11

SiP Assembly and Application using Glass Substrate with Thro...

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11th international microsystems, packaging, assembly and circuits technology conference (impact-IAAC)

作者： Tain, Ra-Min Hu, Dyi-Chung Yang, Kai-Ming Chen, Yu-Hua Wang, Chih-Lun Wang, Cheng-Hsiung Chang, Ching Chang, Yan-bin Ciou, Zih-Yu Hu, Han-Wen Chang, Meng-Fan Unimicron Technol Corp 290 Chung Lun Village Hsinchu 304 Taiwan NTHU Dept Elect Engn 101 Sect 2Kuang Fu Rd Hsinchu 30013 Taiwan

ISBN: (纸本)9781509047697

This paper is to present an assembly structure of system-in-package (SiP) module using the glass substrate with through-glass via (TGV) where the diameter of TGV is 100m and the glass substrate is 200m thick. The glass-substrate is first laminated with a dielectric material on the surface and in through vias;then drill through holes in the dielectric material inside the vias, respectively. The copper is later plated on the wall in the dielectric through hole and on the surface of the dielectric material. This method is called via-in-via (ViV). Two BGA packaged SRAM chips are mounted on the top side of ViV glass substrate to form a ViV SiP module where the two SRAM chips are connected in series with path-delay extraction circuits. The ViV SiP module is mounted on a PCB test board for the measurement of path delay to study the functional performance of the ViV TGV substrate.

关键词： System-in-package

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Simulation Analysis of Structure Design for Low Temperature Cu-Cu Direct Bonding in Heterogeneous Integration and Advanced packaging Systems 13

Simulation Analysis of Structure Design for Low Temperature ...

引用

13th international microsystems, packaging, assembly and circuits technology conference (impact)

作者： Pan, Yu-Ming Yang, Yu-Tao Chou, Tzu-Chieh Yu, Ting-Yang Yang, Kai-Ming Ko, Cheng-Ta Chen, Yu-Hua Tseng, Tzyy-Jang Chen, Kuan-Neng Natl Chiao Tung Univ Dept Elect Engn Hsinchu Taiwan Unimicron Technol Corp Hsinchu Taiwan

ISBN: (纸本)9781538656150

In order to realize Cu-Cu bonding at low temperature, Cu pillar-concave structures on silicon substrate and on silicon substrate with another polymer layer, polyimide (PI), are both investigated through simulation. Height of Cu pillar, thickness of upper and lower silicon substrate, and thickness of Cu concave are simulated in this paper. The proposed structure could have great impacts on current semiconductor packaging technology, such as improvement of joint strength, enhancement of adhesive strength between various substrates, a Cu-Cu bonding process lower than 200 degrees C with simplified manufacturing process.

关键词： Silicon Substrates Stress Bonding Polymers Three-dimensional displays packaging

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Study on the assembly technology of Die-First/Face-Down Type FO-PLP 14

Study on the Assembly Technology of Die-First/Face-Down Type...

引用

14th international microsystems, packaging, assembly and circuits technology conference (impact)

作者： Takekoshi, Masaaki Shimada, Kenji Suzuki, Naoya Nonaka, Toshihisa Hitachi Chem Co Ltd Packaging Solut Ctr Saiwai Ku AIRBIC 3F7-7 Shinkawasaki Kawasaki Kanagawa Japan

ISBN: (纸本)9781728160702

Die shift and passive component drift were the issues of the fabrication of die-first face-down type FO-PLP. Those were investigated in the making process of 515 mm x 510 mm size test vehicle. It was found that there was a strong correlation between the die shift and the CTE of the panel after the temporary bonding adhesive film was removed and the pre-shift technique could reduce the die shift from 5 to less than 1 mu m. 70 of the fabricated packages were electrically connected. In addition, the cause of the passive component drift was made clear. Filler particle with a diameter larger than the gap between the component body and temporary adhesive entered the gap. The drift was greatly suppressed by using the molding compound with the smaller diameter filler and the temporary bonding film of higher adhesion.

关键词： Dies

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