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检索条件"任意字段=International Microsystems Packaging Assembly and Circuits Technology Conference IMPACT"

共 976 条记录，以下是51-60 订阅

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Experimental Study on the Performance of Compact Heat Sink for LSI Packages

Experimental Study on the Performance of Compact Heat Sink f...

引用

7th international microsystems, packaging, assembly and circuits technology conference (impact)

作者： Hatakeyama, Tomoyuki Ishizuka, Masaru Kibushi, Risako Toyama Prefectural Univ Toyama 9390398 Japan

ISBN: (纸本)9781467316385;9781467316354

This paper describes experimental study about cooling performance of natural and forced air convection in compact heat sinks for LSI packages. Temperature rise of several heat sinks having different base areas, fin intervals and fin heights was measured. In natural convection case, the effect of supplied power on the temperature rise of the fin was examined. In forced convection case, correlations between air flow velocity and temperature rise were examined. Further, based on those results, non-dimensional expressions to evaluate cooling performance of compact heat sinks were proposed.

关键词： cooling forced convection heat measurement heat sinks integrated circuit packaging large scale integration natural convection temperature

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CPU Socket Warpage Measurement During Reflow Temperature Variation Using Shadow Moire

CPU Socket Warpage Measurement During Reflow Temperature Var...

引用

4th international microsystems, packaging, assembly and circuits technology conference

作者： Huang Te-Chun Liao Meng-Chieh Tang Hai Inventec Corp Taoyuan Tao Yuan 33547 Taiwan

ISBN: (纸本)9781424443413

When soldering electronic components onto the Printed Circuit Board (PCB), the coplanarity of the solder joints between electronic components and a PCB is a crucial element determining the soldering quality. For those electronic components using solder balls as soldering joints, such as Ball Grid Array (BGA) and CPU socket, component makers or SMT assemblies only can inspect the coplanrity of the solder ball in room temperature. During reflow process, both of components substrate (housing) and PCB warpage will affect solder joint coplanarity. Shadow moire is widely used to measure the warpage of the PCB and electrical assembly components. During soldering stage, the change of the temperature will cause the deformation of electrical assembly components and PCB. The maximum acceptable degree of deformation is clearly defined. As for the components, it only defines the maximum warpage of BGA and Fine Pitch Land Grid Array (FLGA). There is not related regulation of the CPU socket.

关键词： Temperature measurement Sockets Soldering Electronic components assembly Printed circuits Electronics packaging Surface-mount technology Electric variables measurement Land surface temperature

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Failure Analysis for Package of Gold Wire Bonding from Practical Case 17

Failure Analysis for Package of Gold Wire Bonding from Pract...

引用

17th international microsystems, packaging, assembly and circuits technology conference (impact)

作者： Hsieh, Ander Huang, Mike Chen, Johnny C. H. Yeh, Michael Global Ops Proc Tech Div 5 Hsin Ann RdHsinchu Sci Pk Hsinchu 300 Taiwan

ISBN: (数字)9781665452212

ISBN: (纸本)9781665452212

A practical case related to package failure from field was presented in this paper, traditional equipment (cross-section, oven, SEM) was used to reveal 2 of mixed factors that may trigger failure of package. In the final conclusion, we considered the failure was strongly related to crack between gold wire ball & pad and concave molding of package when using 1 similar to 1.5 years from field. Another purpose of this paper is that author would like to draw industry's attention regarding to quality standard of wire bonding. In current standard only stated the pull strength of wire bonding, but it did not control the structure quality of wire bonding, bad connection of electrical property may result in temporal failure of electronic product and not easy to find out the root cause of failure, this situation may influence different level of product, e.g. military, satellite, medical instrument, air industry, server, personal computer.

关键词： Micromechanical devices Gold Ovens Wires packaging Microcomputers Servers

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Fast End-to-end Channel Electrical Characterization Methodology for Design and Manufacture Quality Check 17

Fast End-to-end Channel Electrical Characterization Methodol...

引用

17th international microsystems, packaging, assembly and circuits technology conference (impact)

作者： Hsu, Jimmy Lee, Leo Hsiao, Eric Yang, Joseph Wu, Dian-Ying Wu, Jay Wu, Dong-Han Yang, Tina Chen, Denis Intel Microelect Asia LLC Taiwan Branch 20F369Sec 7Zhong Xiao E Rd Taipei 1156 Taiwan LiTek Technol Co Ltd 4F-318Huannan Rd Pingzhen City 32448 Taoyuan County Taiwan

ISBN: (数字)9781665452212

ISBN: (纸本)9781665452212

This end-to-end methodology from the transmitter, channel to the receiver, is proposed and established for fast, robustness, and accurate PCB characterization to validate design and manufacture quality. The advanced de-embedding with 2x-Thru is adopted to remove the probing effect effectively. Meanwhile, the measurement robustness is validated by intensive repeatability and reproducibility experiments. Through this proposed approach, designers can identify the critical design issues symmetrically and improve the product quality on early design phase by efficient channel loss and system impedance verification.

关键词： Micromechanical devices Transmitters Receivers packaging Robustness Reproducibility of results Product design

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Silicon-based LED packaging Module with Photosensor

Silicon-based LED Packaging Module with Photosensor

引用

7th international microsystems, packaging, assembly and circuits technology conference (impact)

作者： Tseng, Kuochun Tsou, Chingfu Feng Chia Univ Dept Automat Control Engn Taichung 40724 Taiwan

ISBN: (纸本)9781467316385;9781467316354

This study proposes a novel silicon-based LED packaging module with a photo-sensing element. The photosensitive component and the base structure of LED die were directly fabricated on the silicon wafer by microfabrication processes with ion doping and inductively coupled plasma etching processes, respectively, to achieve miniaturization, integration, and low-cost smart LED packaging modules. The subsequent integration of specific heat sinks and thin-shell optical caps facilitates a decrease in operating temperatures and improves sensitivity. Experimental result shows the sensitivity of the sensing module with a chip size of 1x1x0.15 cm(3) was 3.1 mu A/nt. The operating temperatures of the LED die and photosensitive region were maintained below 70 degrees C and 47 degrees C, respectively, when the input current of LED was 0.3 A.

关键词： LED Silicon-based packaging module Microfabrication

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Enhanced System Level Channel Characterization Methodology with Seamless Correlation among Hardware, Signal Integrity and Electrical Validation for Design Robustness 17

Enhanced System Level Channel Characterization Methodology w...

引用

17th international microsystems, packaging, assembly and circuits technology conference (impact)

作者： Hsu, Jimmy Wu, Kuan-Ting Ho, Brian Lin, Lemon Chen, Betty Su, Thonas Wu, Steven Hung, Gary Tseng, Jim Intel Microelect Asia LLC Taiwan Branch 20F369Sec 7Zhong Xiao E Rd Taipei 337 Taiwan

ISBN: (数字)9781665452212

ISBN: (纸本)9781665452212

The proposed methodology demonstrates an effective approach to characterize channel design and closed-loop interactions between electrical validation and signal integrity. By combining the data measured by Intel (R) Automatic In-Board Characterization (AIBC) [1] and the following electrical validation test results, it provides comprehensive correlation between signal integrity and electrical validation, which can efficiently clarify the root cause of issues. As a result, the overall debugging time and effort can decrease and thus accelerate customers' PCB board development.

关键词： Micromechanical devices Industries Correlation Phase measurement Debugging packaging Hardware

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Progress in Transfer of Wafer Level packaging to Panel Format 12

Progress in Transfer of Wafer Level Packaging to Panel Forma...

引用

12th international microsystems, packaging, assembly and circuits technology conference (impact)

作者： Huebner, Henning Ohde, Christian Zoberbier, Ralph Welsh, James Atotech Deutschland GmbH Erassmusstr 20 D-10553 Berlin Germany Atotech Deutschland GmbH Ind Str 69 D-90537 Feucht Germany

ISBN: (纸本)9781538647196

Next generation technologies require new solutions for the packaging industry as Fan-Out Wafer Level packaging (FO-WLP) moves to the Panel Format. Redistribution layers (RDL) for next generation need fine line features of sub 5 mu m lines and spaces without significant yield loss, and tall copper pillar (>100 mu m) plating is requested without increasing the plating time. This simple and straight forward requirement is the providing challenges to the equipment & chemical suppliers in Fan-Out plating technology

关键词： Plating Substrates Additives Anodes packaging Industries

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Minimize Bottom Termination Component Voids by Board assembly Process & Design Optimization 17

Minimize Bottom Termination Component Voids by Board Assembl...

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17th international microsystems, packaging, assembly and circuits technology conference (impact)

作者： Hong, Ling-Ying Li, Yun-Tsung Li, Hsun-Fa Universal Global Sci Ind Co LTD 330 Gongye Rd Nantou 54065 Nantou Taiwan

ISBN: (数字)9781665452212

ISBN: (纸本)9781665452212

Bottom termination component (BTC) is a leadless component with bottom side termination for thermal dissipation on ground pad and signal transmission on isolated pads. There is an exposed die attached pad to contact with the metal pads of printed circuit board (PCB). However, there are many process challenges in board assembly process and solder joint inspection due to hidden ground and signal pads in the package structure. The major difficulty is excessive void formation on bottom side solder joints by bad outgassing without stand-off gap post pick-and-place on solder paste. This paper discusses how to minimize the void size between BTC termination and PCB pads to meet package vendor's or client's void criteria definition by four variables: (1) PCB via configuration with plugged, unplugged, half-plugged type, (2) PCB via array design by matrix/random placement, (3) PCB via position close to pad edge (4) stencil opening ratio. The best combination is found based on Design of Experiment (DoE) result and the BTC void formation in PCB thermal pad is kept significantly < 25%.

关键词： Micromechanical devices Transmission line matrix methods Layout Printed circuits Ink packaging Lead

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Substrate approach for the symphony of IC and packaging

Substrate approach for the symphony of IC and packaging

引用

2008 3rd international microsystems, packaging, assembly and circuits technology conference, impact 2008

作者： James, Ho V.P.

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Next Generation Electroplating technology for High Planarity, Minimum Surface Deposition Microvia Filling

Next Generation Electroplating Technology for High Planarity...

引用

7th international microsystems, packaging, assembly and circuits technology conference (impact)

作者： Yen, Ming-Yao Chiang, Ming-Hung Tai, Hsu-Hsin Chen, Hsien-Chang Yee, Kwok-Wai Li, Crystal Lefebvre, Mark Bayes, Martin Dow Chem Co USA Dow Elect Mat 6Lane 280Chung Shan North Rd Ta Yung Hsiang Taoyuan Hsien Taiwan Lok Tsuen Fanling Hong Kong Peoples R China

ISBN: (纸本)9781467316385;9781467316354

The combination of specialized equipment and new copper via fill chemistry offers end users a cost effective, highly capable and production proven process for IC package substrate microvias filling. A new, insoluble anode, DC microvia fill system is now available for high volume manufacturing (HVM), offering additional operating flexibility and end user preference.

关键词： copper electroplating integrated circuit packaging vias

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