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parallelizing Accelerographic Records processing

Parallelizing Accelerographic Records Processing

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2024 IEEE international parallel and distributed processing symposium Workshops, IPDPSW 2024

作者： Canizales, Ronaldo Mixco, Luis Mcclurg, Jedidiah Colorado State University Department of Computer Science CO United States Observatorio de Amenazas y Recursos Naturales Ministerio de Medio Ambiente y Recursos Naturales El Salvador San Salvador El Salvador

ISBN: (纸本)9798350364606

Strong-motion processing holds paramount importance in earthquake engineering and disaster risk management systems. By leveraging parallel loops and task-parallelism techniques, we address computational challenges posed by large-scale accelerographic datasets. Through experimentation with more than one million data points from six real-world seismic events, our approach achieved speedups of up to 2.9x, demonstrating the effectiveness of parallel programming in accelerating seismic data processing. Our findings highlight the significance of parallel programming techniques in advancing seismological research and enhancing earthquake mitigation strategies. © 2024 IEEE.

关键词： Risk management

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On Higher-performance Sparse Tensor Transposition

On Higher-performance Sparse Tensor Transposition

引用

37th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Guo, Luanzheng Kestor, Gokcen Pacific Northwest Natl Lab Richland WA 99352 USA

ISBN: (纸本)9798350311990

Sparse tensor algebra has been an important tool in scientific research. However, there is limited study on sparse tensor transposition on its performance. To the best of our knowledge, sparse tensor transposition has been a critical performance bottleneck in sparse tensor algebra computations. In this work, we characterize the performance of sparse tensor transposition in a chain of distinct sparse tensor algebra operations and study sparse tensor transposition with, without sorting, and with various sort algorithms. We find that sparse tensor transposition with count sort performs best among other options. However, with the best performant count sort variant, sparse tensor transposition still becomes the performance bottleneck in tensor computations with mixed tensor operation types, such as Sparse-Tensor-Times-Vector (SpTTV). To resolve sparse tensor transpose as a bottleneck, we further investigate possible sparse tensor algorithm designs and propose an efficient new sparse tensor algorithm by integrating bucket sort and count sort. The evaluation results show that our algorithm is faster than the state-of-the-art (SOTA) approach, with 1.2x speedup on average and up to 2.3x speedup with multithreading. There is also potential to further improve the performance of sparse tensor transpose by selectively enabling the SOTA approach or ours on particular dimensions of coordinates with respect to the coordinate distribution.

关键词： parallel sorting algorithm sparse tensor algebra sparse tensor transposition

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Practically Tackling Memory Bottlenecks of Graph-processing Workloads 38

Practically Tackling Memory Bottlenecks of Graph-Processing ...

引用

international parallel and distributed processing symposium (IPDPS)

作者： Jamet, Alexandre Valentin Vavouliotis, Georgios Jimenez, Daniel A. Alvarez, Lluc Casas, Marc Univ Politecn Catalunya UPC Barcelona Supercomputing Ctr BSC Barcelona Spain Huawei Zurich Res Ctr Zurich Switzerland Texas A&M Univ College Stn TX USA

ISBN: (纸本)9798350387117;9798350387124

Graph-processing workloads have become widespread due to their relevance on a wide range of application domains such as network analysis, path-planning, bioinformatics, and machine learning. Graph-processing workloads have massive data footprints that exceed cache storage capacity and exhibit highly irregular memory access patterns due to data-dependent graph traversals. This irregular behaviour causes graph-processing workloads to exhibit poor data locality, undermining their performance. This paper makes two fundamental observations on the memory access patterns of graph-processing workloads: First, conventional cache hierarchies become mostly useless when dealing with graph-processing workloads, since 78.6% of the accesses that miss in the L1 Data Cache (L1D) result in misses in the L2 Cache (L2C) and in the Last Level Cache (LLC), requiring a DRAM access. Second, it is possible to predict whether a memory access will be served by DRAM or not in the context of graph-processing workloads by observing strides between accesses triggered by instructions with the same Program Counter (PC). Our key insight is that bypassing the L2C and the LLC for highly irregular accesses significantly reduces latency cost while also reducing pressure on the lower levels of the cache hierarchy. Based on these observations, this paper proposes the Large Predictor (LP), a low-cost micro-architectural predictor capable of distinguishing between regular and irregular memory accesses. We propose to serve accesses tagged as regular by LP via the standard memory hierarchy, while irregular access are served via the Side Data Cache (SDC). The SDC is a private percore set-associative cache placed alongside the L1D specifically aimed at reducing the latency cost of highly irregular accesses while avoiding polluting the rest of the cache hierarchy with data that exhibits poor locality. SDC coupled with LP yields geometric mean speed-ups of 20.3% and 20.2% on single- and multi-core scenarios, resp

关键词： graph processing cache management off-chip prediction micro-architecture

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QoS-Aware and Cost-Efficient Dynamic Resource Allocation for Serverless ML Workflows 37

QoS-Aware and Cost-Efficient Dynamic Resource Allocation for...

引用

37th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Wu, Hao Deng, Junxiao Fan, Hao Ibrahim, Shadi Wu, Song Jin, Hai Huazhong Univ Sci & Technol Natl Engn Res Ctr Big Data Technol & Syst Serv Comp Technol & Syst Lab Cluster & Grid Comp LabSch Comp Sci & Technol Wuhan Peoples R China Univ Rennes CNRS INRIA IRISA Rennes France

ISBN: (纸本)9798350337662

Machine Learning (ML) workflows are increasingly deployed on serverless computing platforms to benefit from their elasticity and fine-grain pricing. Proper resource allocation is crucial to achieve fast and cost-efficient execution of serverless ML workflows (specially for hyperparameter tuning and model training). Unfortunately, existing resource allocation methods are static, treat functions equally, and rely on offline prediction, which limit their efficiency. In this paper, we introduce CE-scaling - a Cost-Efficient autoscaling framework for serverless ML workflows. During the hyperparameter tuning, CE-scaling partitions resources across stages according to their exact usage to minimize resource waste. Moreover, it incorporates an online prediction method to dynamically adjust resources during model training. We implement and evaluate CE-scaling on AWS Lambda using various ML models. Evaluation results show that compared to state-of-the-art static resource allocation methods, CE-scaling can reduce the job completion time and the monetary cost by up to 63% and 41% for hyperparameter tuning, respectively;and by up to 58% and 38% for model training.

关键词： serverless computing distributed machine learning resource provisioning

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Scalable adaptive algorithms for next-generation multiphase flow simulations 37

Scalable adaptive algorithms for next-generation multiphase ...

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37th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Saurabh, Kumar Ishii, Masado Khanwale, Makrand A. Sundar, Hari Ganapathysubramanian, Baskar Iowa State Univ Dept Mech Engn Ames IA 50011 USA Univ Utah Sch Comp Salt Lake City UT USA Stanford Univ Ctr Turbulence Res Stanford CA USA

ISBN: (纸本)9798350337662

High-fidelity flow simulations are indispensable when analyzing systems exhibiting multiphase flow phenomena. The accuracy of multiphase flow simulations is strongly contingent upon the finest mesh resolution used to represent the fluid-fluid interfaces. However, the increased resolution comes at a higher computational cost. In this work, we propose algorithmic advances that aim to reduce the computational cost without compromising on the physics by selectively detecting key regions of interest (droplets/filaments) that require significantly higher resolution. The framework uses an adaptive octree-based meshing framework that is integrated with PETSc's linear algebra solvers. We demonstrate scaling of the framework up to 114,688 processes on TACC's Frontera. Finally, we deploy the framework to simulate one of the most resolved simulations of primary jet atomization. This simulation - equivalent to 35 trillion grid points on a uniform grid - is 64x larger than current state-of-the-art simulations and provides unprecedented insights into an important flow physics problem with a diverse array of engineering applications.

关键词： multiphase flow simulations octree massively parallel algorithms adaptive mesh

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Scheduling with Many Shared Resources 37

Scheduling with Many Shared Resources

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37th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Deppert, Max A. Jansen, Klaus Maack, Marten Pukrop, Simon Rau, Malin Univ Kiel Dept Comp Sci Kiel Germany Paderborn Univ Paderborn Heinz Nixdorf Inst Paderborn Germany Paderborn Univ Dept Comp Sci Paderborn Germany

ISBN: (纸本)9798350337662

Consider the many shared resources scheduling problem where jobs have to be scheduled on identical parallel machines with the goal of minimizing the makespan. However, each job needs exactly one additional shared resource in order to be executed and hence prevents the execution of jobs that need the same resource while being processed. Previously, an approximation ratio of asymptotically 2 was the best known result for this problem. Furthermore, a 6/5-approximation for the case with only two machines was known as well as a PTAS for the case with a constant number of machines. We present a simple and fast 5/3-approximation and a much more involved but still reasonable 1.5-approximation. Furthermore, we provide a PTAS for the case with only a constant number of machines, which is arguably simpler and faster than the previously known one, as well as a PTAS with resource augmentation for the general case. The approximation schemes make use of the N-fold integer programming machinery, which has found more and more applications in the field of scheduling recently. It is plausible that the latter results can be improved and extended to more general cases. Lastly, we give an inapproximability result for the natural problem extension where each job may need up to a constant number of different resources, namely 3, ruling out better than 5/4 approximations for that case.

关键词： Scheduling Approximation parallel Identical Machines Resource Constraints Conflicts

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AnyQ: An Evaluation Framework for Massively-parallel Queue Algorithms 37

AnyQ: An Evaluation Framework for Massively-Parallel Queue A...

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37th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Kenzel, Michael Lemme, Stefan Membarth, Richard Kurtenacker, Matthias Devillerst, Hugo Steinberger, Markus Slusallek, Philipp Deutsch Forschungszentrum Kfinstliche Intelligenz Saarland Informat Campus Kaiserslautern Germany Tech Hsch Ingolstadt THI Res Inst Almot Bavaria Ingolstadt Germany Univ Saarland Saarland Informat Campus Saarbrucken Germany Graz Univ Technol Graz Austria

ISBN: (纸本)9798350337662

Concurrent queue algorithms have been subject to extensive research. However, the target hardware and evaluation methodology on which the published results for any two given concurrent queue algorithms are based often share only minimal overlap. A meaningful comparison is, thus, exceedingly difficult. With the continuing trend towards more and more heterogeneous systems, it is becoming more and more important to not only evaluate and compare novel and existing queue algorithms across a wider range of target architectures, but to also be able to continuously re-evaluate queue algorithms in light of novel architectures and capabilities. To address this need, we present AnyQ, an evaluation framework for concurrent queue algorithms. We design a set of programming abstractions that enable the mapping of concurrent queue algorithms and benchmarks to a wide variety of target architectures. We demonstrate the effectiveness of these abstractions by showing that a queue algorithm expressed in a portable, high-level manner can achieve performance comparable to handcrafted implementations. We design a system for testing and benchmarking queue algorithms. Using the developed framework, we investigate concurrent queue algorithm performance across a range of both CPU as well as GPU architectures. In hopes that it may serve the community as a starting point for building a common repository of concurrent queue algorithms as well as a base for future research, all code and data is made available as open source software at https://***/anyq.

关键词： Massively parallel Concurrent Queue GPU

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Neural Network Compiler for parallel High-Throughput Simulation of Digital Circuits 37

Neural Network Compiler for Parallel High-Throughput Simulat...

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37th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Gavier, Ignacio Russell, Joshua Patel, Devdhar Rietman, Edward Siegelmann, Hava Univ Massachusetts Manning Coll Informat & Comp Sci Amherst MA 01003 USA

ISBN: (纸本)9798350337662

Register Transfer Level (RTL) simulation and verification of Digital Circuits are extremely important and costly tasks in the Integrated Circuits industry. While some simulators have incorporated the exploitation of parallelism in the structure of Digital Circuits to run on multi-core CPUs, the maximum throughput they achieve quickly reaches a plateau, as described by Amdahl's Law. Recent research from Nvidia has obtained much higher throughput in simulations using GPUs, highlighting the potential of these devices for Digital Circuit simulation. However, they were required to incorporate sophisticated algorithms to support GPU simulation. In addition, the unbalanced structure of real-life Digital Circuits provides difficulties for processing on multi-threaded devices. In this paper, we present a Digital Circuit compiler that utilizes Neural Networks to exploit the various parallelisms in RTL simulation, making use of PyTorch, a widely-used Neural Network framework that facilitate their simulation on GPUs. By using properties of Boolean Functions, we developed a novel algorithm that converts any Digital Circuit into a Neural Network, and optimization techniques that help in pushing the thread computational capability to the limit. The results show three orders of magnitude higher throughput than Verilator RTL simulator, an improvement of one order of magnitude compared to the state-of-the-art GPU techniques from Nvidia. We believe that the use of Neural Networks not only provides a significant improvement in simulation and verification tasks in the Integrated Circuits industry, but also opens a line of research for simulators at the logic and physical gate level.

关键词： Integrated Circuits Design and Verification of Digital Circuits RTL Synthesis and Simulation Neural Network Representation parallel Computation GPU

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A Domain-Specific Language for Reconfigurable, distributed Software Architecture

A Domain-Specific Language for Reconfigurable, Distributed S...

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37th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Zhu, Henry Zhao, Junyong Sultana, Nik Univ Illinois Dept Comp Sci Urbana IL USA Univ Arizona Dept Comp Sci Tucson AZ USA Illinois Inst Technol Dept Comp Sci Chicago IL USA

ISBN: (纸本)9798350311990

A program's architecture-how it organizes the invocation of application-specific logic-influences important program characteristics including its scalability and security. Architecture details are usually expressed in the same programming language as the rest of a program, and can be difficult to distinguish from non-architecture code. And once defined, architecture is difficult and risky to change because it couples tightly with application logic over time. We introduce C-Saw: an approach to express a software's architecture using a new embedded domain-specific language (EDSL) designed for that purpose. It decouples application-specific logic from architecture, making it easier to identify architectural details of software. C-Saw leverages three ideas: (i) introducing a new, formally-specified EDSL to separate an application's architecture description from its programming language;(ii) reducing architecture implementation to the definition and management of distributed key-value tables, and (iii) introducing an expressive state-management abstraction for distributed applications. We describe a prototype implementation of C-Saw for C programs and use it to build end-to-end examples of expressing and changing the architecture of widely-used, third-party software. We evaluate this on Redis, cURL, and Suricata and find that C-Saw provides expressiveness and reusability, requires fewer lines of code when compared to directly using C to express architectural patterns, and imposes low performance overhead on typical workloads.

关键词： Key-Value Tables Process Algebra Coordination Language Domain-Specific Language

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A Task Based Approach for Co-Scheduling Ensemble Workloads on Heterogeneous Nodes

A Task Based Approach for Co-Scheduling Ensemble Workloads o...

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37th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Kamatar, Alok Friese, Ryan Gioiosa, Roberto Univ Chicago Dept Comp Sci Chicago IL 60637 USA Pacific Northwest Natl Lab HPC Grp Richland WA USA

ISBN: (纸本)9798350311990

Scientific workflows consist of multiple, connected applications, with data and results flowing from one to another in a pipeline. Traditionally, such workflows are executed in sequential order, storing intermediate data in storage disks. Co-scheduling application workflows concurrently on the same compute nodes would greatly reduce the cost of moving data to/from storage and allow real-time analysis of intermediate results. Nevertheless, most parallel programming runtimes do not allow seamless integration of various applications in a scientific workflow, in part due to the complexity of managing data and resources. The situation is even more complicated for heterogeneous systems. In this work we extend the Minos Computing Library (MCL) runtime to accelerate pipe-lined and parallel workloads where multiple applications are running in the same system. MCL's asynchronous task library and runtime dynamically manages resources to allow co-scheduling of multiple processes sharing heterogeneous resources. In addition, we design a custom extension of the Open Compute Language (OpenCL) to enable multiple processes to share device memory. We enable MCL to coordinate these shared buffers to allow for easy, fast data sharing between applications. Using malleable micro-benchmarks and two application workflows that combine scientific simulation and AI-based analysis, we show that our method outperforms traditional approaches.

关键词： parallel systems Scheduling and Task Partitioning Heterogeneous Systems Workflow management

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