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检索条件"任意字段=International Parallel and Distributed Processing Symposium"

共 11369 条记录，以下是171-180 订阅

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Introducing parallel Computing in a Second CS Course 36

Introducing Parallel Computing in a Second CS Course

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Newhall, Tia Webb, Kevin C. Chaganti, Vasanta Danner, Andrew Swarthmore Coll Comp Sci Dept Swarthmore PA 19081 USA

ISBN: (纸本)9781665497473

The ubiquity of multicore processors, cloud computing, and hardware accelerators have elevated parallel and distributed computing (PDC) topics into fundamental building blocks of the undergraduate CS curriculum. Therefore, it is increasingly important for students to learn a common core of introductory PDC topics and develop parallel thinking skills early in their CS studies. We present the curricular design, pedagogy, and goals of an introductory-level course on computer systems that introduces parallel computing to students who have only a CS1 background. Our course focuses on three curricular goals that serve to integrate the ACM-IEEE TCPP guidelines throughout: a vertical slice through the computer of how it runs a program;evaluating system costs associated with running a program;and taking advantage of the power of parallel computing. We elaborate on the goals and details of our course's key modules, and we discuss our pedagogical approach that includes active-learning techniques. We find that the PDC foundation gained through early exposure in this course helps students gain confidence in their ability to expand and apply their understanding of PDC concepts throughout their CS education.

关键词： parallel and distributed computing CS Education curriculum design

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A Family of Fast parallel Greedy Algorithms for the Steiner Forest Problem 36

A Family of Fast Parallel Greedy Algorithms for the Steiner ...

引用

36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Ghalami, Laleh Grosu, Daniel Wayne State Univ Dept Comp Sci Detroit MI 48202 USA

ISBN: (纸本)9781665497473

We introduce a family of fast parallel greedy algorithms for the Steiner Forest Problem, a fundamental combinatorial optimization problem in graphs. Given an undirected graph with non-negative weights for edges and a set of pairs of vertices called terminals, the Steiner Forest Problem is to find the minimum cost subgraph that connects each of the terminal pairs together. We design a family of parallel algorithms based on a sequential heuristic greedy algorithm called Paired Greedy which iteratively connects the terminal pairs that have the minimum distance. The family of parallel algorithms consists of a set of algorithms exhibiting various degrees of parallelism determined by the number of pairs that are connected in parallel in each iteration of the algorithms. We implement and run the algorithms on a multi-core system and perform an extensive experimental analysis. The results show that our proposed parallel algorithms achieve significant speedup with respect to the sequential Paired Greedy algorithm and provide solutions with costs that are very close to those of the solutions obtained by the sequential Paired Greedy algorithm.

关键词： Steiner forest parallel algorithms multi-core

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Locality-aware Qubit Routing for the Grid Architecture 36

Locality-aware Qubit Routing for the Grid Architecture

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Banerjee, Avah Liang, Xin Tohid, R. Missouri S&T Dept Comp Sci Rolla MO 65409 USA Louisiana State Univ Ctr Computat & Technol Baton Rouge LA 70803 USA

ISBN: (纸本)9781665497473

Due to the short decohorence time of qubits available in the NISQ-era, it is essential to pack (minimize the size and or the depth of) a logical quantum circuit as efficiently as possible given a sparsely coupled physical architecture. In this work we introduce a localityaware qubit routing algorithm based on a graph theoretic framework. Our algorithm is designed for the grid and certain "grid-like" architectures. We experimentally show the competitiveness of algorithm by comparing it against the approximate token swapping algorithm, which is used as a primitive in many state-of-the-art quantum transpilers. Our algorithm produces circuits of comparable depth (better on random permutations) while being an order of magnitude faster than a typical implementation of the approximate token swapping algorithm.

关键词： qubit routing parallel token swapping grid graphs

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Dynamic Batch parallel Algorithms for Updating PageRank 36

Dynamic Batch Parallel Algorithms for Updating PageRank

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Sahu, Subhajit Kothapalli, Kishore Banerjee, Dip Sankar Int Inst Informat Technol Hyderabad Hyderabad India Indian Inst Technol Jodhpur Jodhpur Rajasthan India

ISBN: (纸本)9781665497473

The design and implementation of parallel algorithms for dynamic graph problems is attracting significant research attention in the recent years, driven by numerous applications to social network analysis, neuroscience, and protein interaction networks. One such problem is the computation of PageRank values of vertices in a directed graph. This paper presents two new parallel algorithms for recomputing the PageRank values of vertices in a dynamic graph. Our techniques require the recomputation of the PageRank of only the vertices affected by the insertion/deletion of a batch of edges. We conduct detailed experimental studies of our algorithm on a set of 11 real-world graphs. Our results on Intel Xeon Silver 4116 CPU and NVIDIA Tesla V100 PCIe 16GB GPU indicate that our algorithms outperform static and dynamic update algorithms by 6.1x and 8.6x on the CPU, and by 9.8x and 9.3x on the GPU respectively. We also compare the performance of the algorithms in batched mode to cumulative single-edge updates.

关键词： Proteins Silver distributed processing Neuroscience Social networking (online) Heuristic algorithms Graphics processing units

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parallel Tensor Train Rounding using Gram SVD 36

Parallel Tensor Train Rounding using Gram SVD

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Al Daas, Hussam Ballard, Grey Manning, Lawton Rutherford Appleton Lab Computat Math Grp Didcot Oxon England Wake Forest Univ Dept Comp Sci Winston Salem NC 27101 USA

ISBN: (纸本)9781665481069

Tensor Train (TT) is a low-rank tensor representation consisting of a series of three-way cores whose dimensions specify the TT ranks. Formal tensor train arithmetic often causes an artificial increase in the TT ranks. Thus, a key operation for applications that use the TT format is rounding, which truncates the TT ranks subject to an approximation error guarantee. Truncation is performed via SVD of a highly structured matrix, and current rounding methods require careful orthogonalization to compute an accurate SVD. We propose a new algorithm for TT-Rounding based on the Gram SVD algorithm that avoids the expensive orthogonalization phase. Our algorithm performs less computation and can be parallelized more easily than existing approaches, at the expense of a slight loss of accuracy. We demonstrate that our implementation of the rounding algorithm is efficient, scales well, and consistently outperforms the existing state-of-the-art parallel implementation in our experiments.

关键词： distributed processing Tensors Scalability Approximation algorithms Approximation error Matrix decomposition Iterative methods

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A Locality-aware Cooperative distributed Memory Caching for parallel Data Analytic Applications 36

A Locality-aware Cooperative Distributed Memory Caching for ...

引用

36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Hung, Chia-Ting Chou, Jerry Chen, Ming-Hung Chung, I-Hsin Natl Tsing Hua Univ Comp Sci Dept Hsinchu Taiwan IBM TJ Watson Res Ctr New York NY USA

ISBN: (纸本)9781665497473

Memory caching has long been used to fill up the performance gap between processor and disk for reducing the data access time of data-intensive computations. Previous studies on caching mostly focus on optimizing the hit rate of a single machine. But in this paper, we argue that the caching decision of a distributed memory system should be performed in a cooperative manner for the parallel data analytic applications, which are commonly used by emerging technologies, such as Big Data and AI (Artificial Intelligence), to perform data mining and sophisticated analytics on larger data volume in a shorter time. A parallel data analytic job consists of multiple parallel tasks. Hence, the completion time of a job is bounded by its slowest task, meaning that the job cannot benefit from caching until all inputs of its tasks are cached. To address the problem, we proposed a cooperative caching design that periodically rearranges the cache placement among nodes according to the data access pattern while taking the task dependency and network locality into account. Our approach is evaluated by a trace-driven simulator using both synthetic workload and real-world traces. The results show that we can reduce the average completion times up to 33% compared to a non-collaborative caching polices and 25% compared to other start-of-the-art collaborative caching policies.

关键词： parallel Data processing Caching Algorithm Performance distributed Systems

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Combined Application of Approximate Computing Techniques in DNN Hardware Accelerators 36

Combined Application of Approximate Computing Techniques in ...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Russo, Enrico Palesi, Maurizio Patti, Davide Lahdhiri, Habiba Monteleone, Salvatore Ascia, Giuseppe Catania, Vincenzo Univ Catania Catania Italy Niccolo Cusano Univ Rome Italy ESIEE Paris Noisy Le Grand France

ISBN: (纸本)9781665497473

This paper applies Approximate Computing (AC) techniques to the main elements which form a DNN hardware accelerator, namely, computation, communication, and memory subsystems. Specifically, approximate multipliers for computation, link voltage swing reduction for communication, voltage over-scaling for the internal SRAM memory, and lossy compression of the external DRAM memory are considered. The different AC techniques are applied in isolation as well as in conjunction with each other. A set of representative CNN models are mapped onto the approximated hardware accelerators and the trade-offs performance vs. energy vs. accuracy are derived for the execution of CNN inferences.

关键词： distributed processing Conferences Computational modeling Approximate computing Random access memory Voltage Hardware acceleration

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distributed Aerial 3D Object Mapping Reconstruction Using Message Passing Interface 26

Distributed Aerial 3D Object Mapping Reconstruction Using Me...

引用

26th international Electronics symposium (IES) on Shaping the Future - Society 5.0 and Beyond

作者： Arissabarno, Cahyo Winarno, Idris Sukaridhoto, Sritrusta Politekn Elekt Negeri Surabaya Dept Informat & Comp Engn Surabaya Indonesia

ISBN: (纸本)9798350392005;9798350391992

Aerial reconstruction of 3D object mapping involves utilizing drones or Unmanned Aerial Vehicles (UAVs) equipped with cameras to capture images for high-resolution 3D model reconstruction of various objects and terrains. This technique is applicable across various fields, such as Urban Planning, Vehicle Navigation, Environmental Studies, Civil Engineering, and Cultural Heritage Conservation. Drones capture hundreds of overlapping aerial photos, which are then processed to generate photorealistic 3D representations of topographic surfaces using photogrammetry software. However, the reconstruction process is time-consuming and computationally intensive, especially when processing large datasets. This research addresses these challenges by employing parallel computing using the Message Passing Interface (MPI) to distribute the computational workload across multiple nodes. By utilizing MPI, the computational tasks are efficiently divided among four nodes, significantly reducing processing time and alleviating the burden on individual CPUs. The study demonstrates that parallel computing with MPI reduces the reconstruction time from 74 minutes to 27 minutes, achieving a speedup of 2.74 times. This research demonstrates a novel application of MPI to the domain of aerial 3D reconstruction, achieving a specific and substantial reduction in processing time. Additionally, it provides insights into future enhancements, such as parallel texture reconstruction and automation of translation processes.

关键词： Message Passing Interface parallel Computing MPI 3D Reconstruction Aerial 3D Object Mapping

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A Scalable parallel Partition Tridiagonal Solver for Many-Core and Low B/F Processors 36

A Scalable Parallel Partition Tridiagonal Solver for Many-Co...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Mitsuda, Tatsuya Ono, Kenji Kyushu Univ Grad Sch Fukuoka Japan Kyushu Univ Fac Informat Sci & Elect Engn Fukuoka Japan Kyushu Univ Res Inst Informat & Technol Fukuoka Japan

ISBN: (纸本)9781665497473

Tridiagonal systems are among the most fundamental computations in science, engineering, and mathematics, and one solver used in such systems is Tree Partitioning Reduction (TPR), which is a divide-and-conquer method that solves large-scale linear equations by dividing them and then computing the parts in parallel within different local memory threads. Herein, we propose an improved TPR algorithm that has a parallel cyclic reduction flavor, with which we reduced the number of algorithm steps by approximately half while simultaneously increasing arithmetic intensity and cache reusability. A performance evaluation conducted on an Intel Skylake-SP microprocessor showed a high hit ratio for the L1 cache and that our solver was as much as 31 times faster on 32 threads for 262144 equations. In the case of a Nvidia Tesla P100 GPU, our method processed 10 MRow/s more than TPR and cuSPARSE.

关键词： Tridiagonal system GPU parallel computing Multi/many-core

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Low-bit CUTLASS GEMM Template Auto-tuning using Neural Network 22

Low-bit CUTLASS GEMM Template Auto-tuning using Neural Netwo...

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22nd IEEE international symposium on parallel and distributed processing with Applications, ISPA 2024

作者： Guo, Hong Guo, Nianhui Meinel, Christoph Yang, Haojin University of Potsdam Hasso Plattner Institute Potsdam Germany

ISBN: (纸本)9798331509712

Optimizing General Matrix Multiplication (GEMM) on GPU platforms has become increasingly important due to the scaling demands of modern deep neural network research. While substantial progress has been made in accelerating high-precision GEMM, optimizing lower-bit GEMM remains an open problem. The CUTLASS library offers highly optimized low-bit GEMM based on tensor cores, but performance varies significantly with tile and pipeline settings across different GPUs. We introduce a novel auto-tuning framework for low-bit CUTLASS GEMM that employs a neural network model to predict optimal GEMM template parameters for target GPUs. This model was trained on a synthetic dataset featuring various matrix sizes from different Ampere GPUs and evaluated on these GPUs. In the test dataset, our method achieved an accuracy of up to 92.9%. Real-time evaluations of low-bit data types on the A100 GPU demonstrated speedups of up to 2.03× for GEMM and 1.44× for the linear layer compared to the default templates. © 2024 IEEE.

关键词： Graphics processing unit

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