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检索条件"任意字段=International Parallel and Distributed Processing Symposium"

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Low-bit CUTLASS GEMM Template Auto-tuning using Neural Network 22

Low-bit CUTLASS GEMM Template Auto-tuning using Neural Netwo...

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22nd IEEE international symposium on parallel and distributed processing with Applications, ISPA 2024

作者： Guo, Hong Guo, Nianhui Meinel, Christoph Yang, Haojin University of Potsdam Hasso Plattner Institute Potsdam Germany

ISBN: (纸本)9798331509712

Optimizing General Matrix Multiplication (GEMM) on GPU platforms has become increasingly important due to the scaling demands of modern deep neural network research. While substantial progress has been made in accelerating high-precision GEMM, optimizing lower-bit GEMM remains an open problem. The CUTLASS library offers highly optimized low-bit GEMM based on tensor cores, but performance varies significantly with tile and pipeline settings across different GPUs. We introduce a novel auto-tuning framework for low-bit CUTLASS GEMM that employs a neural network model to predict optimal GEMM template parameters for target GPUs. This model was trained on a synthetic dataset featuring various matrix sizes from different Ampere GPUs and evaluated on these GPUs. In the test dataset, our method achieved an accuracy of up to 92.9%. Real-time evaluations of low-bit data types on the A100 GPU demonstrated speedups of up to 2.03× for GEMM and 1.44× for the linear layer compared to the default templates. © 2024 IEEE.

关键词： Graphics processing unit

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Fast Convergence to Fairness for Reduced Long Flow Tail Latency in Datacenter Networks 36

Fast Convergence to Fairness for Reduced Long Flow Tail Late...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Snyder, John Lebeck, Alvin R. Duke Univ Dept Comp Sci Durham NC 27706 USA

ISBN: (纸本)9781665481069

Many data-intensive applications, such as distributed deep learning and data analytics, require moving vast amounts of data between compute servers in a distributed system. To meet the demands of these applications, datacenters are adopting Remote Direct Memory Access (RDMA), which has higher bandwidth and lower latency than traditional kernel-based networking. To ensure high performance of RDMA networks, congestion control manages queue depth on switches, and historically focused on moderating queue depth to ensure small flows complete quickly. Unfortunately, one side-effect of many common decisions is that large flows are starved of bandwidth. This negatively impacts the flow completion time (FCT) of large, bandwidth-bound flows, which are integral to the performance of data-intensive applications. The FCT is particularly impacted at the tail, which is increasingly critical for predictable application performance. We identify the root causes of the poor performance for long flows and measure the impact. We then design mechanisms that improve long flow FCT without compromising small flow performance. Our evaluations show that these improvements reduce 99.9% tail FCT of long flows by over 2x.

关键词： distributed processing Protocols Additives distributed databases Tail Bandwidth Throughput

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Optimization of Compiler-Generated OpenCL CNN Kernels and Runtime for FPGAs 36

Optimization of Compiler-Generated OpenCL CNN Kernels and Ru...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Chung, Seung-Hun Abdelrahman, Tarek S. Univ Toronto Edward S Rogers Sr Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

ISBN: (纸本)9781665497473

We translate frozen CNN models into OpenCL kernels with the TVM compiler and then use Intel's OpenCL SDK to compile to an FPGA bitstream. We improve the performance of the generated base hardware with optimizations that increase parallelism, reduce memory access latency, and save on-chip resources. We automate these optimizations in TVM and evaluate them by generating accelerators for LeNet-5, MobileNetVl and ResNet-34 on an Intel Stratix 10SX. The optimizations improve the performance of the generated accelerators by up to 846 x over the base ones. The optimized accelerators are up to 4.57 x faster than TensorFlow on CPU, 3.83x faster than single-threaded TVM and are only 0.34x slower than TVM with 56 threads. Our optimized kernels also outperform ones generated by similar approaches that use high-level synthesis, but they underperform ones that utilize hand-optimized designs. Thus, our approach is most useful in environments that benefit from increased performance and fast prototyping, realizing the benefits of FPGAs without hardware design expertise.

关键词： distributed processing Runtime Conferences parallel processing Hardware System-on-chip Kernel

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DEAN: A Lightweight and Resource-efficient Blockchain Protocol for Reliable Edge Computing 36

DEAN: A Lightweight and Resource-efficient Blockchain Protoc...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Al-Mamun, Ahdullah Shen, Haoting Zhao, Dongfang Univ Nevada Reno NV 89557 USA

ISBN: (纸本)9781665481069

Edge computing draws a lot of recent research interests because of the performance improvement by offloading many workloads from the remote data center to nearby edge nodes. Nonetheless, one open challenge of this emerging paradigm lies in the potential security issues on edge nodes. This paper proposes a cooperative protocol, namely DEAN, equipped with a unique resource-efficient quorum building mechanism to adopt blockchain seamlessly in an edge computing infrastructure to prevent data manipulation and allow fair data sharing with quick recovery under resource constraints of limited storage, computing, and network capacity. Specifically, DEAN leverages a parallel mechanism equipped with three independent core components, effectively achieving low resource consumption while allowing secured parallel block processing on edge nodes. We have implemented a system prototype based on DEAN and experimentally verified its effectiveness with a comparison with four popular blockchain implementations: Ethereum, Parity, IOTA, and Hyperledger Fabric. Experimental results show that the system prototype exhibits high resilience to arbitrary failures. Performance-wise, DEAN-based blockchain implementation outperforms the state-of-the-art blockchain systems with up to 88.6x higher throughput and 26x lower latency.

关键词： Edge computing Blockchains distributed computing Consensus protocols

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Fully Dynamic Line Maintenance by Hybrid Programmable Matter 36

Fully Dynamic Line Maintenance by Hybrid Programmable Matter

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Nokhanji, Nooshin Flocchini, Paola Santoro, Nicola Carleton Univ Sch Comp Sci Ottawa ON Canada Univ Ottawa Sch Elect Engn & Comp Sci Ottawa ON Canada

ISBN: (纸本)9781665497473

Motivated by the manipulation of nanoscale materials, recent investigations have focused on hybrid systems where passive elements incapable of movement, called tiles, are manipulated by one or more mobile entities, called robots, with limited computational capabilities. Like in most self-organizing systems, the fundamental concern is with the (geometric) shapes created by the position of the tiles;among them, the line is perhaps the most important. The existing investigations have focused on formation of the shape, but not on its reconfiguration following the failure of some of the tiles. In this paper, we study the problem of maintaining a line formation in presence of fully dynamic failures: any tile can stop functioning at any time. We show how this problem can be solved by a group of very simple robots, with the computational power of deterministic finite automata.

关键词： Shape formation fault-tolerance hybrid programmable matter line maintenance distributed algorithms self-assembly

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APC-SCA: A Fully-parallel Annealing Algorithm with Autonomous Pinning Effect Control 36

APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomou...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Okonogi, Daiki Jimbo, Satoru Ando, Kota Thiem Van Chu Yu, Jaehoon Motomura, Masato Kawamura, Kazushi Tokyo Inst Technol AI Comp Res Unit Yokohama Kanagawa Japan

ISBN: (纸本)9781665497473

Annealing computation has recently attracted attention as it can efficiently solve various combinatorial optimization problems using an Ising model. Stochastic cellular automata annealing (SCA) is a promising algorithm that can realize fast spin-update by utilizing its parallel computing capability. However, in SCA, preparing an appropriate control of the pinning parameter is a hard task, which degrades its usability. This paper proposes a novel approach called APC-SCA (Autonomous Pinning effect Control SCA) where the spin pinning parameter can be controlled autonomously by observing individual spin flips. The evaluation results using max-cut and N-queen problems demonstrate that the proposed approach can obtain better solutions than the conventional approach with a grid search of optimal pinning parameter control.

关键词： combinatorial optimization cellular automata stochastic algorithm parallel annealing Ising model

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Falcon: A Timestamp-based Protocol to Maximize the Cache Efficiency in the distributed Shared Memory 36

Falcon: A Timestamp-based Protocol to Maximize the Cache Eff...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Zhang, Jin Yu, Xiangyao Qi, Zhengwei Guan, Haibing Shanghai Jiao Tong Univ Shanghai Peoples R China Univ Wisconsin Madison WI USA

ISBN: (纸本)9781665481069

distributed shared memory (DSM) systems can handle data-intensive applications and recently receiving more attention. A majority of existing DSM implementations are based on write-invalidation (WI) protocols, which achieve sub-optimal performance when the cache size is small. Specifically, the vast majority of invalidation messages become useless when evictions are frequent. The problem is troublesome regarding scarce memory resources in data centers. To this end, we propose a self-invalidation protocol Falcon to eliminate invalidation messages. It relies on per-operation timestamps to achieve the global memory order required by sequential consistency (SC). Furthermore, we conduct a comprehensive discussion on the two protocols with an emphasis on the cache size impact. We also implement both protocols atop a recent DSM system, Grappa. The evaluation shows that the optimal protocol can improve the performance of a KV database by 27% and a graph processing application by 71.4% against the vanilla cache-free scheme.

关键词： distributed shard memory cache coherence self-invalidation

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In-Memory Indexed Caching for distributed Data processing 36

In-Memory Indexed Caching for Distributed Data Processing

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Uta, Alexandru Ghit, Bogdan Dave, Ankur Rellermeyer, Jan Boncz, Peter Leiden Univ LIACS Leiden Netherlands Databricks San Francisco CA USA Univ Calif Berkeley Berkeley CA USA Delft Univ Technol Delft Netherlands CWI Amsterdam Netherlands

ISBN: (纸本)9781665481069

Powerful abstractions such as dataframes are only as efficient as their underlying runtime system. The de-facto distributed data processing framework, Apache Spark, is poorly suited for the modern cloud-based data-science workloads due to its outdated assumptions: static datasets analyzed using coarse-grained transformations. In this paper, we introduce the Indexed DataFrame, an in-memory cache that supports a dataframe abstraction which incorporates indexing capabilities to support fast lookup and join operations. Moreover, it supports appends with multi-version concurrency control. We implement the Indexed DataFrame as a lightweight, standalone library which can be integrated with minimum effort in existing Spark programs. We analyze the performance of the Indexed DataFrame in cluster and cloud deployments with real-world datasets and benchmarks using both Apache Spark and Databricks Runtime. In our evaluation, we show that the Indexed DataFrame significantly speeds-up query execution when compared to a nonindexed dataframe, incurring modest memory overhead.

关键词： distributed processing Runtime Data analysis Cluster computing Relational databases Libraries Concurrency control

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Sequre: a high-performance framework for rapid development of secure bioinformatics pipelines 36

Sequre: a high-performance framework for rapid development o...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Smajlovic, Haris Shajii, Ariya Berger, Bonnie Cho, Hyunghoon Numanagic, Ibrahim Univ Victoria Victoria BC Canada MIT Cambridge MA 02139 USA Broad Inst MIT & Harvard Cambridge MA 02142 USA

ISBN: (纸本)9781665497473

Genomic data leaks are irreversible. Leaked DNA cannot be changed, stays disclosed indefinitely, and affects the owner's family members as well. The recent large-scale genomic data collections [1], [2] render the traditional privacy protection mechanisms, like the Health Insurance Portability and Accountability Act (HIPAA), inadequate for protection against the novel security attacks [3]. On the other hand, data access restrictions hinder important clinical research that requires large datasets to operate [4]. These concerns can be naturally addressed by the employment of privacy-enhancing technologies, such as a secure multiparty computation (MPC) [5]–[10]. Secure MPC enables computation on data without disclosing the data itself by dividing the data and computation between multiple computing parties in a distributed manner to prevent individual computing parties from accessing raw data. MPC systems are being increasingly adopted in fields that operate on sensitive datasets [11]–[13], such as computational genomics and biomedical research [14]–[22].

关键词： distributed processing Data privacy Pipelines Employment distributed databases Genomics Insurance

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Topological Modeling and parallelization of Multidimensional Data on Microelectrode Arrays 36

Topological Modeling and Parallelization of Multidimensional...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Tawose, Olamide Timothy Li, Bin Yang, Lei Yan, Feng Zhao, Dongfang Univ Nevada Dept Comp Sci & Engn Reno NV 89557 USA

ISBN: (纸本)9781665481069

Microelectrode arrays (MEAs) are physical devices widely used in various science and engineering fields. One common computational challenge when applying a high-density MEA (i.e., a larger number of wires, more accurate locations of abnormal cells) is how to efficiently compute those resistance values provided the nonlinearity of the system of equations with the unknown resistance values per the Kirchhoff law. This paper proposes an algebraic-topological model for MEAs such that we can identify the intrinsic parallelism that cannot be identified by conventional approaches. We implement a system prototype called Parma based on the proposed topological methodology. Experimental results show that Parma outperforms the state-of-the-practice in time, scalability and memory usage: the computation time is two orders of magnitude faster on up to 1,024 cores with almost linear scalability and the memory is much better utilized with proportionally less warm-up time with respect to the number of concurrent threads.

关键词： multidimensional data parallel processing scientific computing applied topology

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