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Shared-Memory parallel Algorithms for Fully Dynamic Maintenance of 2-Connected Components 36

Shared-Memory Parallel Algorithms for Fully Dynamic Maintena...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Haryan, Chirayu Anant Ramakrishna, G. Kothapalli, Kishore Banerjee, Dip Sankar Indian Inst Technol Tirupati Tirupati Andhra Pradesh India Int Inst Informat Technol Hyderabad Hyderabad India Indian Inst Technol Jodhpur Jodhpur Rajasthan India

ISBN: (纸本)9781665481069

Finding the biconnected components of a graph has a large number of applications in many other graph problems including planarity testing, computing the centrality metrics, finding the (weighted) vertex cover, coloring, and the like. Recent years saw the design of efficient algorithms for this problem across sequential and parallel computational models. However, current algorithms do not work in the setting where the underlying graph changes over time in a dynamic manner via the insertion or deletion of edges. the insertion or deletion of edges. Dynamic algorithms in the sequential setting that obtain the biconnected components of a graph upon insertion or deletion of a single edge are known from over two decades ago. parallel algorithms for this problem are not heavily studied. In this paper, we design shared-memory parallel algorithms that obtain the biconnected components of a graph subsequent to the insertion or deletion of a batch of edges. Our algorithms hence will be capable of exploiting the parallelism adduced due to a batch of updates. We implement our algorithms on an AMD EPYC 7742 CPU having 128 cores. Our experiments on a collection of 10 realworld graphs from multiple classes indicate that our algorithms outperform parallel state-of-the-art static algorithms.

关键词： Semiconductor device modeling Measurement distributed processing Heuristic algorithms Instruction sets Computational modeling Maintenance engineering

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Scalable Data parallel distributed Training for Graph Neural Networks 36

Scalable Data Parallel Distributed Training for Graph Neural...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Koyama, Sohei Tatebe, Osamu Univ Tsukuba Tsukuba Ibaraki Japan

ISBN: (纸本)9781665497473

Graph neural networks (GNNs) operate on data represented as graphs, and are useful for a wide variety of tasks from chemical reaction and protein structure prediction to content recommendation systems. However, training for large graphs and improving training performance remain significant challenges. Existing distributed training systems partition a graph among all compute nodes to train for large graphs;however, this results in a communication overhead to degrade training performance. In this study, to solve these two problems, we propose a scalable data-parallel distributed GNN training system designed to partition a graph redundantly. It is implemented using remote direct memory access (RDMA) and nonblocking active messages to efficiently utilize network performance and hide communication overhead by overlapping with the training computation. Experimental results are presented to show the strong scalability of the proposed approach, which achieved parallel efficiencies of 0.93 using eight compute nodes for the ogbn-products dataset in the Open Graph Benchmark (OGB) and 0.95 based on two compute nodes using 32 compute nodes for the ogbn-papersl00M dataset. The proposed system exhibited a training performance 18.9% better than the state-of-the-art DistDGL, even with only a single compute node. The results demonstrate that the proposed approach may be considered a promising method to achieve scalable training performance for large graphs.

关键词： Graph Neural Networks distributed training High Performance Computing Deep Graph Library

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QGIP: A Framework Bridging Quantum Grayscale Image processing and Applications 22

QGIP: A Framework Bridging Quantum Grayscale Image Processin...

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22nd IEEE international symposium on parallel and distributed processing with Applications, ISPA 2024

作者： Che, Xilong Zhang, Jiale Chen, Shuo Peng, Shun Hu, Juncheng Jilin University College of Computer Science and Technology Changchun China

ISBN: (纸本)9798331509712

Quantum computing offers parallel processing capabilities and resource-saving advantages, particularly useful for managing expansive datasets and complex image processing tasks. Grayscale images, being the simplest single-channel image mode, are frequently employed in artificial intelligence training. Before actual image applications, various image processing operations are typically required. However, the restoration of a grayscale image of dimensions 2n × 2n after a series of linear transformations poses a challenge. Existing methods typically involve finding the inverse of the most recent linear transformation or re-encoding the image followed by repeated operations until the final transformation, resulting in excessive computational overhead and disconnection from subsequent quantum grayscale image applications. To address this issue, we propose a universal quantum linear restoration algorithm for grayscale image, denoted as QLR, which effectively bridges the stages of linear transformation and subsequent image applications. QLR reduces the time complexity from O(2n) to O(n) compared to classical counterpart. Building upon the QLR algorithm, we further propose two quantum resource-optimized compression methods for optional lossless image storage. Combining with other quantum algorithms and techniques, we design a framework (QGIP) aimed at bridging the processes of quantum grayscale image processing and applications. Experiments simulated on the IBM Quantum platform validate the correctness and efficiency of our proposal. © 2024 IEEE.

关键词： Image reconstruction

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Compiler -Driven SWAR parallelism for High -Performance Bitboard Algorithms

Compiler -Driven SWAR Parallelism for High -Performance Bitb...

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Fey, Florian Gorlatch, Sergei Univ Munster Munster Germany

ISBN: (纸本)9798350364613;9798350364606

parallel high-performance computing relies on cache -efficient, branch-free algorithms that are often expressed as imperative computations over multi-dimensional arrays. Numerous problem domains, spanning from image processing to graph analytics, and from state space exploration in combinatorial optimization to computer Chess, require carefully crafted algorithms that capitalize on patterns inherent in the underlying problem structure. A renowned technique, SIMD-Within-A-Register (SWAR), harnesses integer arithmetic to attain significant hardware parallelism. However, this approach typically demands labor-intensive efforts from domain experts with specialized knowledge of the underlying hardware architecture. We therefore present a compiler-driven approach that automates the transformation of conventional array -based C-code into highly tuned integer arithmetic, exploiting SWAR parallelism without the requirement of tedious manual optimization efforts. Our approach achieves substantial performance improvements, exhibiting an average speedup of 30x compared to conventional array-based implementations.

关键词： High-Performance Computing Cache-Efficient Algorithms parallel Computing SWAR SIMD-parallelism Compiler-Driven Optimization

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Benchmarking Quantum Processor Performance through Quantum Distance Metrics Over An Algorithm Suite 36

Benchmarking Quantum Processor Performance through Quantum D...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Stein, Samuel Wiebe, Nathan Ang, James Li, Ang Pacific Northwest Natl Lab Richland WA 99352 USA

ISBN: (纸本)9781665497473

Quantum computing is poised to solve computational paradigms that classical computing could never feasibly reach. Tasks such as prime factorization to Quantum Chemistry are examples of classically difficult problems that have analogous algorithms that are sped up on quantum computers. To attain this computational advantage, we must first traverse the noisy intermediate scale quantum (NISQ) era, in which quantum processors suffer from compounding noise factors that can lead to unreliable algorithm induction producing noisy results. We describe QASMBench, a suite of QASM-level (Quantum assembly language) benchmarks that challenge all realisable angles of quantum processor noise. We evaluate a large portion of these algorithms by performing density matrix tomography on 14 IBMQ Quantum devices.

关键词： Performance evaluation Computers distributed processing Program processors Quantum chemistry Conferences Benchmark testing

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Scaling and Selecting GPU Methods for All Pairs Shortest Paths (APSP) Computations 36

Scaling and Selecting GPU Methods for All Pairs Shortest Pat...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Xia, Yang Jiang, Peng Agrawal, Gagan Ramnath, Rajiv Ohio State Univ Comp Sci & Engn Columbus OH 43210 USA Univ Iowa Comp Sci Dept Iowa City IA 52242 USA Augusta Univ Comp & Cyber Sci Augusta GA USA

ISBN: (纸本)9781665481069

All Pairs Shortest Path (APSP) is one of the graph problems where the output size is significantly larger than the input size. This paper examines the issues in scaling GPU implementations for this problem beyond the memory limits. Because the existing (in-core) methods offer a complex trade-off between the overall computation complexity and the available parallelism, choosing the best out-of-core version for a given matrix is challenging. We develop three efficient out-of-core implementations, which are based on the blocked Floyd-Warshall algorithm, Johnson's algorithm, and the boundary algorithm, respectively. Next, we develop a methodology to select the best implementation for a given graph. Experimental results show that compared with an efficient multi-core APSP implementation, the out-of-core version achieves speedups of 8.22 to 12.40 for graphs with a small separator, and speedups of 2.23 to 2.79 for other sparse graphs, and our models can select the best implementation in most cases.

关键词： distributed processing Costs Particle separators Computational modeling Graphics processing units parallel processing Distance measurement

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parallel Assembly Sequence Planning Based on Sparrow Search Algorithms 22

Parallel Assembly Sequence Planning Based on Sparrow Search ...

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22nd IEEE international symposium on parallel and distributed processing with Applications, ISPA 2024

作者： He, Haichen Liu, Weibin Zhang, Yinan Song, Shasha Cheng, Yue Liu, Ziheng Xing, Weiwei Beijing Jiaotong University School of Computer Science and Technology China Crrc Information Technology Co. Ltd. China Beijing Jiaotong University School of Software Engineering China

ISBN: (纸本)9798331509712

Assembly sequence planning (ASP) is the most important process in the product lifecycle. This paper aims to propose a parallel assembly sequence planning method based on sparrow search algorithm (SSA) to improve the assembly quality and efficiency. The proposed method divides the problem into assembly unit division (AUD) part and ASP part. In AUD part, we use the markov clustering algorithm (MCA) to solve the AUD problem. In ASP part, the ASP evaluation system is designed for the assembly part sequence planning (APSP) problem and assembly unit sequence planning (AUSP) problem, and the discrete artificial sparrow search algorithm (DASSA) is proposed for solving the discrete APSP problem. The results of comparison experiment verify the effectiveness of the proposed method. Compared with genetic algorithm (GA) and particle swarm optimization (PSO), the proposed DASSA gets the optimal results and fastest convergence. The method proposed solves ASP problem to efficiently perform parallel assembly sequence planning and reduce production time, making it cost-effective in intelligent manufacturing. © 2024 IEEE.

关键词： Particle swarm optimization (PSO)

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Dynamic Task Shaping for High Throughput Data Analysis Applications in High Energy Physics 36

Dynamic Task Shaping for High Throughput Data Analysis Appli...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Tovar, Ben Lyons, Ben Mohrman, Kelci Sly-Delgado, Barry Lannon, Kevin Thain, Douglas Univ Notre Dame Dept Comp Sci & Engn Notre Dame IN 46556 USA Univ Notre Dame Dept Phys Notre Dame IN 46556 USA

ISBN: (纸本)9781665481069

distributed data analysis frameworks are widely used for processing large datasets generated by instruments in scientific fields such as astronomy, genomics, and particle physics. Such frameworks partition petabyte-size datasets into chunks and execute many parallel tasks to search for common patterns, locate unusual signals, or compute aggregate properties. When well-configured, such frameworks make it easy to churn through large quantities of data on large clusters. However, configuring frameworks presents a challenge for end users, who must select a variety of parameters such as the blocking of the input data, the number of tasks, the resources allocated to each task, and the size of nodes on which they run. If poorly configured, the result may perform many orders of magnitude worse than optimal, or the application may even fail to make progress at all. Even if a good configuration is found through painstaking observations, the performance may change drastically when the input data or analysis kernel changes. This paper considers the problem of automatically configuring a data analysis application for high energy physics (TopEFT) built upon standard frameworks for physics analysis (Coffea) and distributed tasking (Work Queue). We observe the inherent variability within the application, demonstrate the problems of poor configuration, and then develop several techniques for automatically sizing tasks to meet goals of resource consumption, and overall application completion.

关键词： distributed processing High energy physics Data analysis Instruments Genomics Throughput Task analysis

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RSCache: A Tail Latency Friendly Cache Based on NVMe SSDs 22

RSCache: A Tail Latency Friendly Cache Based on NVMe SSDs

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22nd IEEE international symposium on parallel and distributed processing with Applications, ISPA 2024

作者： Lu, Jincheng Cai, Miao Ye, Baoliu Hohai University College of Computer Science and Software Engineering Nanjing China Nanjing University of Aeronautics and Astronautics College of Computer Science and Technology Nanjing China Nanjing University State Key Laboratory for Novel Software Technology Nanjing China

ISBN: (纸本)9798331509712

High fan-out requests are prevalent in systems employing multi-tier architectures. These requests are divided into several sub-requests for parallel processing. However, a high fan-out request must await all sub-requests to be completed before returning, but the processing times of sub-requests are unpredictable due to their differences in characteristics, such as data volume and data popularity. Meanwhile, existing SSD-based caches struggle to adjust request processing speeds to ensure timely handling. As a result, some sub-requests are delayed, affecting the overall latency and causing long tail latency *** paper proposes RSCache, a tail latency-friendly cache based on NVMe SSDs. RSCache combines the NVMe Weighted Round-robin (WRR) arbitration mechanism with a priority-based scheduling mechanism to enable differentiated request processing. We propose a fan-out size-based priority assignment strategy along with a latency-aware sub-request sorting method. They collaborate to prioritize sub-requests according to their impacts on tail latency and schedule them to NVMe priority queues with various processing speeds, effectively reducing the processing time variations among sub-requests. In addition, we balance the load across queues to avoid congestion with a novel feedback mechanism. We implement the prototype of RSCache based on SPDK. Our experiments demonstrate that RSCache reduces tail latency by up to 40% and improves throughput by two times compared to state-of-the-art SSD-based cache designs. © 2024 IEEE.

关键词： parallel architectures

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Performance Analysis of parallel FFT on Large Multi-GPU Systems 36

Performance Analysis of Parallel FFT on Large Multi-GPU Syst...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Ayala, Alan Tomov, Stan Stoyanov, Miroslav Haidar, Azzam Dongarra, Jack Univ Tennessee Knoxville TN 37996 USA Oak Ridge Natl Lab Oak Ridge TN USA Nvidia Corp Santa Clara CA USA Univ Manchester Manchester Lancs England

ISBN: (纸本)9781665497473

In this paper we present a performance study of multidimensional Fast Fourier Transforms (FFT) with GPU accelerators on modern hybrid architectures, as those expected for upcoming exascale systems. We assess and leverage features from traditional implementations of parallel FFTs and provide an algorithm that encompasses a wide range of their parameters, and adds novel developments such as FFT grid shrinking and batched transforms. Next, we create a bandwidth model to quantify the computational costs and analyze the well-known communication bottleneck for All-to-All and Point-to-Point MPI exchanges. Then, using a tuning methodology, we are able to accelerate the FFT computation and reduce the communication cost, achieving linear scalability on a large-scale system with GPU accelerators. Finally, our performance analysis is extended to show that carefully tuning the algorithm can further accelerate applications heavily relying on FFTs, such is the case of molecular dynamics software. Our experiments were performed on Summit and Spock supercomputers with IBM Power9 cores, over 3000 NVIDIA V-100 GPUs, and AMD MI-100 GPUs.

关键词： FFT Multi-GPU MPI tuning Scalability

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