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An On-the-Fly Method to Exchange Vector Clocks in distributed-Memory Programs 36

An On-the-Fly Method to Exchange Vector Clocks in Distribute...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Schwitanski, Simon Tomski, Felix Protze, Joachim Terboven, Christian Mueller, Matthias S. Rhein Westfal TH Aachen IT Ctr Aachen Germany

ISBN: (纸本)9781665497473

Vector clocks are logical timestamps used in correctness tools to analyze the happened-before relation between events in parallel program executions. In particular, race detectors use them to find concurrent conflicting memory accesses, and replay tools use them to reproduce or find alternative execution paths. To record the happened-before relation with vector clocks, tool developers have to consider the different synchronization concepts of a programming model, e.g., barriers, locks, or message exchanges. Especially in distributed-memory programs, various concepts result in explicit and implicit synchronization between processes. Previously implemented vector clock exchanges are often specific to a single programming model, and a translation to other programming models is not trivial. Consequently, analyses relying on the vector clock exchange remain model-specific. This paper proposes an abstraction layer for on-the-fly vector clock exchanges for distributed-memory programs. Based on the programming models MPI, OpenSHMEM, and GASPI, we define common synchronization primitives and explain how model-specific procedures map to our model-agnostic abstraction layer. The exchange model is general enough also to support synchronization concepts of other parallel programming models. We present our implementation of the vector clock abstraction layer based on the Generic Tool Infrastructure with translators for MPI and OpenSHMEM. In an overhead study using the SPEC MPI 2007 benchmarks, the slowdown of the implemented vector clock exchange ranges from 1.1x to 12.6x for runs with up to 768 processes.

关键词： Vector clock distributed memory synchronization correctness tools MPI OpenSHMEM GASPI

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mpisee: MPI Profiling for Communication and Communicator Structure 36

mpisee: MPI Profiling for Communication and Communicator Str...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Vardas, Ioannis Hunold, Sascha Ajanohoun, Jordy, I Traeff, Jesper Larsson TU Wien Res Grp Parallel Comp Fac Informat Vienna Austria

ISBN: (纸本)9781665497473

Cumulative performance profiling is a fast and lightweight method for gaining summary information about where and how communication time in parallel MPI applications is spent. MPI provides mechanisms for implementing such profilers that can be transparently used with applications. Existing profilers typically profile on a process basis and record the frequency, total time, and volume of MPI operations per process. This can lead to grossly misleading cumulative information for applications that make use of MPI features for partitioning the processes into different communicators. We present a novel MPI profiler, mpisee, for communicator-centric profiling that separates and records collective and pointto-point communication information per communicator in the application. We discuss the implementation of mpisee which makes significant use of the MPI attribute mechanism. We evaluate our tool by measuring its overhead and profiling a number of standard applications. Our measurements with thirteen MPI applications show that the overhead of mpisee is less than 3 %. Moreover, using mpisee, we investigate in detail two particular MPI applications, SPLATT and GROMACS, to obtain information on the various MPI operations for the different communicators of these applications. Such information is not available by other, state-of-the-art profilers. We use the communicator-centric information to improve the performance of SPLATT resulting in a significant runtime decrease when run with 1024 processes.

关键词： Time-frequency analysis distributed processing Runtime Scalability Conferences Benchmark testing Topology

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The Logarithmic Random Bidding for the parallel Roulette Wheel Selection with Precise Probabilities

The Logarithmic Random Bidding for the Parallel Roulette Whe...

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Nakano, Koji Hiroshima Univ Grad Sch Adv Sci & Engn Kagamiyama 1-4-1 Higashihiroshima 7398527 Japan

ISBN: (纸本)9798350364613;9798350364606

The roulette wheel selection is a critical process in heuristic algorithms, enabling the probabilistic choice of items based on assigned fitness values. It selects an item with a probability proportional to its fitness value. This technique is commonly employed in ant-colony algorithms to randomly determine the next city to visit when solving the traveling salesman problem. Our study focuses on parallel algorithms designed to select one of multiple processors, each associated with fitness values, using random wheel selection. We propose a novel approach called logarithmic random bidding, which achieves an expected runtime logarithmic to the number of processors with non-zero fitness values, using the CRCW-PRAM model with a shared memory of constant size. Notably, the logarithmic random bidding technique demonstrates efficient performance, particularly in scenarios where only a few processors are assigned non-zero fitness values.

关键词： roulette wheel selection fitness proportionate selection ant colony optimization traveling salesman problem parallel heuristic algorithms

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Modeling Memory Contention between Communications and Computations in distributed HPC Systems 36

Modeling Memory Contention between Communications and Comput...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Denis, Alexandre Jeannot, Emmanuel Swartvagher, Philippe Inria Bordeaux Sud Ouest Bordeaux France

ISBN: (纸本)9781665497473

To amortize the cost of MPI communications, distributed parallel HPC applications can overlap network communications with computations in the hope that it improves global application performance. When using this technique, both computations and communications are running at the same time. But computation usually also performs some data movements. Since data for computations and for communications use the same memory system, memory contention may occur when computations are memory-bound and large messages are transmitted through the network at the same time. In this paper we propose a model to predict memory band-width for computations and for communications when they are executed side by side, according to data locality and taking contention into account. Elaboration of the model allowed to better understand locations of bottleneck in the memory system and what are the strategies of the memory system in case of contention. The model was evaluated on many platforms with different characteristics, and showed a prediction error in average lower than 4 %.

关键词： HPC MPI Memory Contention NUMA Band-width Predictive Models Multicore processing

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Accelerating SLIDE: Exploiting Sparsity on Accelerator Architectures 36

Accelerating SLIDE: Exploiting Sparsity on Accelerator Archi...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Ko, Sho Rucker, Alexander Zhang, Yaqi Mure, Paul Olukotun, Kunle Stanford Univ Stanford CA 94305 USA SambaNova Syst Palo Alto CA USA

ISBN: (纸本)9781665497473

A significant trend in machine learning is sparsifying the training of neural networks to reduce the amount of computation required. Algorithms like Sub-LInear Deep learning Engine (SLIDE) [2] use locality-sensitive hashing (LSH) to create sparsity. These sparse training algorithms were originally developed on multi-threaded multicore CPUs. However, they are not well-studied and optimized for accelerator platforms such as GPUs and reconfigurable dataflow architectures (RDAs). In this paper, we study the different variants of the SLIDE algorithm and investigate accuracy-performance tradeoffs on CPU, GPU, and RDAs. The implementation targeting RDA outperforms the GPU by 7.5x. The performance on a limited-memory RDA is improved further by proposing a smart caching algorithm, which is 2 x faster than the baseline RDA. Furthermore, we are able to achieve another 2 x performance by putting all of the weights on-chip using an RDA with enough memory. We believe our work will pave the road for the future development of both algorithm and hardware architecture for sparse training.

关键词： Training Machine learning algorithms Multicore processing Roads Neurons Graphics processing units Random access memory

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Shared-Memory parallel Dynamic Louvain Algorithm for Community Detection

Shared-Memory Parallel Dynamic Louvain Algorithm for Communi...

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Sahu, Subhajit Kothapalli, Kishore Banerjee, Dip Sankar Int Inst Informat Technol Hyderabad Hyderabad 500032 India Indian Inst Tehnol Jodhpur Surpura Bypass Rd Karwar 342030 Rajasthan India

ISBN: (纸本)9798350364613;9798350364606

Community detection refers to the identification of coherent partitions in networks. In this poster, we present a parallel dynamic Louvain algorithm that finds conummities in rapidly evolving graphs. Given a batch update of edge deletions or insertions, our algorithm identifies an approximate set of affected vertices in the graph with minimal overhead and updates the community membership of each vertex. This process repeats until convergence. Our approach achieves a mean speedup of 7.3 x, compared to our parallel and optimized implementation of Delta-screening combined with Louvain, a recently proposed stateof-the-art approach.

关键词： Population dynamics

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A distributed Automatic Domain-Specific Multi-Word Term Recognition Architecture using Spark Ecosystem 22

A Distributed Automatic Domain-Specific Multi-Word Term Reco...

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22nd international symposium on parallel and distributed Computing, ISPDC 2023

作者： Truica, Ciprian-Octavian Istrate, Neculai-Ovidiu Apostol, Elena-Simona University Politehnica of Bucharest Faculty of Automatic Control and Computers Computer Science and Engineering Department Bucharest Romania

ISBN: (纸本)9798350341270

Automatic Term Recognition is used to extract domain-specific terms that belong to a given domain. In order to be accurate, these corpus and language-dependent methods require large volumes of textual data that need to be processed to extract candidate terms that are afterward scored according to a given metric. To improve text preprocessing and candidate terms extraction and scoring, we propose a distributed Spark-based architecture to automatically extract domain-specific terms. The main contributions are as follows: (1) propose a novel distributed automatic domain-specific multi-word term recognition architecture built on top of the Spark ecosystem;(2) perform an in-depth analysis of our architecture in terms of accuracy and scalability;(3) design an easy-to-integrate Python implementation that enables the use of Big Data processing in fields such as Computational Linguistics and Natural Language processing. We prove empirically the feasibility of our architecture by performing experiments on two real-world datasets. © 2023 IEEE.

关键词： Ecosystems

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distributed Checkpointing in Dataflow with Static Scheduling 35

Distributed Checkpointing in Dataflow with Static Scheduling

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35th IEEE international symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

作者： Alves, Tiago A. O. Univ Estado Rio De Janeiro Rio De Janeiro Brazil

ISBN: (纸本)9798350381603

The Dataflow model, where instructions or tasks are fired as soon as their input data is ready, was proven to be a good fit for parallel/distributed computation. Previous works have presented DFER (Dataflow Error Recovery Model), that allows transient error and recovery in dataflow by adding special tasks and edges to the dataflow graph itself. However, permanent faults or faults that cause a processing element (PE) to become irresponsive are not addressed by DFER. For those cases it is necessary to adopt a checkpointing method. Since the whole purpose of Dataflow is to achieve high levels of parallelism and explore the potential asynchronicity between PEs, it is clear that the checkpointing method adopted must be uncoordinated and distributed. Current algorithms for distributed checkpointing rely solely on guaranteeing that causality between checkpoints can be trackable. In the context of Dataflow with static scheduling, i.e. when the dataflow graph is partitioned among the available PEs at compile-time, causality trackability is not sufficient as we will show. Since static scheduling of dataflow graphs is very important in various scenarios, it calls for a new algorithm for distributed checkpointing that can be adopted for the execution of statically scheduled dataflow graphs. In this paper we describe why the ability to track causality is not enough for statically scheduled dataflow and introduce a new algorithm for distributed checkpointing specifically tailored for such model of execution.

关键词： dataflow distributed checkpointing fault tolerance parallel programming

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Multi-View Learning for parallelism Discovery of Sequential Programs 36

Multi-View Learning for Parallelism Discovery of Sequential ...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Chen, Le Mahmud, Quazi Ishtiaque Jannesari, Ali Iowa State Univ Dept Comp Sci Ames IA 50011 USA

ISBN: (纸本)9781665497473

Identifying suitable parallelizable regions in sequential programs is a crucial task for performance optimizations. Traditional methods like static and dynamic analysis have flaws like insufficient accuracy or high overhead runtime. Recent studies are more interested in applying machine learning techniques to this topic. The crux of parallelism discovery with machine learning is to generate meaningful code representations. One promising route is to exploit the dependence graph through Graph Neural Networks (GNNS). In this paper, a novel multi-view framework is proposed to automatically detect potential parallelism opportunities. Sequential programs are first represented by program execution graphs encompassing both semantic and structural information. Then two independent views are defined: namely, a structural pattern view and a node feature view. In the structural view, local graph structural patterns are captured via random anonymous walks and then fed into a Graph Convolutional Network (GCN). The node features, both dynamic and static, are fed into another GCN in the node feature view. In addition, a multi-view model is designed to unify the node features and the structural features for parallelism detection. Our approach achieves comparable state-of-the-art performance on parallel region classification with an accuracy up to 92.6% when evaluated with popular parallel computing benchmarks.

关键词： machine learning artificial intelligence parallel program language

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AxoNN: An asynchronous, message-driven parallel framework for extreme-scale deep learning 36

AxoNN: An asynchronous, message-driven parallel framework fo...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Singh, Siddharth Bhatele, Abhinav Univ Maryland Dept Comp Sci College Pk MD 20742 USA

ISBN: (纸本)9781665481069

In the last few years, the memory requirements to train state-of-the-art neural networks have far exceeded the DRAM capacities of modern hardware accelerators. This has necessitated the development of efficient algorithms to train these neural networks in parallel on large-scale GPU-based clusters. Since computation is relatively inexpensive on modern GPUs, designing and implementing extremely efficient communication in these parallel training algorithms is critical for extracting the maximum performance. This paper presents AxoNN, a parallel deep learning framework that exploits asynchrony and message-driven execution to schedule neural network operations on each GPU, thereby reducing GPU idle time and maximizing hardware efficiency. By using the CPU memory as a scratch space for offloading data periodically during training, AxoNN is able to reduce GPU memory consumption by four times. This allows us to increase the number of parameters per GPU by four times, thus reducing the amount of communication and increasing performance by over 13%. When tested against large transformer models with 12-100 billion parameters on 48-384 NVIDIA Tesla V100 GPUs, AxoNN achieves a per-GPU throughput of 49.4-54.78% of theoretical peak and reduces the training time by 2237 days (15-25% speedup) as compared to the state-of-the-art.

关键词： parallel deep learning asynchrony message driven scheduling memory optimizations

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