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Bounding the Flow Time in Online Scheduling with Structured processing Sets 36

Bounding the Flow Time in Online Scheduling with Structured ...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Canon, Louis-Claude Dugois, Anthony Marchal, Loris Univ Franche Comte FEMTO ST Inst Besancon France ENS Lyon INRIA LIP Lyon France ENS Lyon INRIA CNRS LIP Lyon France

ISBN: (纸本)9781665481069

Replication in distributed key-value stores makes scheduling more challenging, as it introduces processing set restrictions, which limits the number of machines that can process a given task. We focus on the online minimization of the maximum response time in such systems, that is, we aim at bounding the latency of each task. When processing sets have no structure, Anand et al. (Algorithmica, 2017) derive a strong lower bound on the competitiveness of the problem: no online scheduling algorithm can have a competitive ratio smaller than Omega(m), where m is the number of machines. In practice, data replication schemes are regular, and structured processing sets may make the problem easier to solve. We derive new lower bounds for various common structures, including inclusive, nested or interval structures. In particular, we consider fixed sized intervals of machines, which mimic the standard replication strategy of key-value stores. We prove that EFT (Earliest Finish Time) scheduling is (3 - 2/k)-competitive when optimizing max-flow on disjoint intervals of size k. However, we show that the competitive ratio of EFT is at least m - k + 1 when these intervals overlap, even when unit tasks are considered. We compare these two replication strategies in simulations and assess their efficiency when popularity biases are introduced, i.e., when some machines are accessed more frequently than others because they hold popular data. Even though overlapping intervals suffer from a bad worst-case in theory, they enable clusters to reach a maximum load that is up to 50% higher than with disjoint sets.

关键词： Flow Time Lower Bound Restricted Assignment processing Set Restrictions Replication Key-Value Stores

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A General Offloading Approach for Near-DRAM processing-In-Memory Architectures 36

A General Offloading Approach for Near-DRAM Processing-In-Me...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Chen, Dan Jin, Hai Zheng, Long Huang, Yu Yao, Pengcheng Gui, Chuangyi Wang, Qinggang Liu, Haifeng He, Haiheng Liao, Xiaofei Zheng, Ran Huazhong Univ Sci & Technol Natl Engn Res Ctr Big Data Technol & Syst Serv Comp Technol & Syst Lab Clusters & Grid Comp Lab Wuhan Peoples R China

ISBN: (纸本)9781665481069

processing-in-memory (PIM) is promising to solve the well-known data movement challenge by performing in-situ computations near the data. Leveraging PIM features is pretty profitable to boost the energy efficiency of applications. Early studies mainly focus on improving the programmability for computation offloading on PIM architectures. They lack a comprehensive analysis of computation locality and hence fail to accelerate a wide variety of applications. In this paper, we present a general-purpose instruction-level offloading technique for near-DRAM PIM architectures, namely IOTPIM, to exploit PIM features comprehensively. IOTPIM is novel with two technical advances: 1) a new instruction offloading policy that fully considers the locality of the whole on-chip cache hierarchy, and 2) an offloading performance benefit prediction model that directly predicts offloading performance benefits of an instruction based on the input dataset characterizes, preserving low analysis overheads. The evaluation demonstrates that IOTPIM can be applied to accelerate a wide variety of applications, including graph processing, machine learning, and image processing. IOTPIM outperforms the state-of-the-art PIM offloading techniques by 1.28x-1.51x while ensuring offloading accuracy as high as 91.89% on average.

关键词： processing-in-memory PIM offloading technique data locality

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Teaching parallel Algorithms Using the Binary-Forking Model

Teaching Parallel Algorithms Using the Binary-Forking Model

引用

1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Blelloch, Guy E. Gu, Yan Sun, Yihan Carnegie Mellon Univ Pittsburgh PA 15213 USA Univ Calif Riverside Riverside CA 92521 USA

ISBN: (纸本)9798350364613;9798350364606

In this paper, we share our experience in teaching parallel algorithms with the binary-forking model. With hardware advances, multicore computers are now ubiquitous. This has created a substantial demand in both research and industry to harness the capabilities of parallel computing. It is thus important to incorporate parallelism in computer science education, especially in the early stages of the curriculum. However, it is commonly believed that understanding and using parallelism requires a deep understanding of computer systems and architecture, which complicates introducing parallelism to young students and non-experts. We propose to use the binary-forking model in teaching parallel algorithms, proposed by our previous research work. This model is meant to capture the performance of algorithms on modern multicore shared-memory machines, which is a simple abstraction to isolate algorithm design ideas with system-level details. The abstraction allows for simple analysis based on the work-span model in theory, and can be directly implemented as parallel programs in practice. In this paper, we briefly overview some basic primitives in this model, and provide a list of algorithms that we believe are well-suited in parallel algorithm courses.

关键词： binary-forking model computer science education fork-join parallel algorithms parallel programming

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A Methodology to Build Decision Analysis Tools Applied to distributed Reinforcement Learning 36

A Methodology to Build Decision Analysis Tools Applied to Di...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Prigent, Cedric Cudennec, Loic Costan, Alexandru Antoniu, Gabriel Univ Rennes INRIA CNRS IRISA Rennes France DGA Maitrise Informat Rennes France

ISBN: (纸本)9781665497473

As Artificial Intelligence-based applications become more and more complex, speeding up the learning phase (which is typically computation-intensive) becomes more and more necessary. distributed machine learning (ML) appears adequate to address this problem. Unfortunately, ML also brings new development frameworks, methodologies and high-level programming languages that do not fit to the regular high-performance computing design flow. This paper introduces a methodology to build a decision making tool that allows ML experts to arbitrate between different frameworks and deployment configurations, in order to fulfill project objectives such as the accuracy of the resulting model, the computing speed or the energy consumption of the learning computation. The proposed methodology is applied to an industrial-grade case study in which reinforcement learning is used to train an autonomous steering model for a cargo airdrop system. Results are presented within a Pareto front that lets ML experts choose an appropriate solution, a framework and a deployment configuration, based on the current operational situation. While the proposed approach can effortlessly be applied to other machine learning problems, as for many decision making systems, the selected solutions involve a trade-off between several antagonist evaluation criteria and require experts from different domains to pick the most efficient solution from the short list. Nevertheless, this methodology speeds up the development process by clearly discarding, or, on the contrary, including combinations of frameworks and configurations, which has a significant impact for time and budget-constrained projects.

关键词： Machine Learning distributed Computing Decision Making

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Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications 29

Dalorex: A Data-Local Program Execution and Architecture for...

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29th IEEE international symposium on High-Performance Computer Architecture (HPCA)

作者： Orenes-Vera, Marcelo Tureci, Esin Wentzlaff, David Martonosi, Margaret Princeton Univ Princeton NJ 08544 USA

ISBN: (纸本)9781665476522

Applications with low data reuse and frequent irregular memory accesses, such as graph or sparse linear algebra workloads, fail to scale well due to memory bottlenecks and poor core utilization. While prior work with prefetching, decoupling, or pipelining can mitigate memory latency and improve core utilization, memory bottlenecks persist due to limited off-chip bandwidth. Approaches doing processing in-memory (PIM) with Hybrid Memory Cube (HMC) overcome bandwidth limitations but fail to achieve high core utilization due to poor task scheduling and synchronization overheads. Moreover, the high memory-per-core ratio available with HMC limits strong scaling. We introduce Dalorex, a hardware-software co-design that achieves high parallelism and energy efficiency, demonstrating strong scaling with >16,000 cores when processing graph and sparse linear algebra workloads. Over the prior work in PIM, both using 256 cores, Dalorex improves performance and energy consumption by two orders of magnitude through (1) a tile-based distributed-memory architecture where each processing tile holds an equal amount of data, and all memory operations are local;(2) a task-based parallel programming model where tasks are executed by the processing unit that is co-located with the target data;(3) a network design optimized for irregular traffic, where all communication is one-way, and messages do not contain routing metadata;(4) novel traffic-aware task scheduling hardware that maintains high core utilization;and (5) a data-placement strategy that improves work balance. This work proposes architectural and software innovations to provide the greatest scalability to date for running graph algorithms while still being programmable for other domains.

关键词： distributed scalable parallel data-local near-memory architecture sparse graph NoC network bandwidth

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Efficient Erasure-Coded Data Recovery Based on Machine Learning With a Low Level of Storage Overhead 22

Efficient Erasure-Coded Data Recovery Based on Machine Learn...

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22nd IEEE international symposium on parallel and distributed processing with Applications, ISPA 2024

作者： Zhao, Xiaobo Wei, Bing Luo, Ning Chen, Qian Wu, Yi Zhang, Shudong Zhou, Lijuan Hainan University School of Cyberspace Security Haikou China Hainan University School of International Communication and Arts Haikou China

ISBN: (纸本)9798331509712

distributed storage systems typically use erasure codes for fault tolerance to reduce storage overhead. However, the data repair process in erasure-coded systems can generate heavy I/O overhead. Existing methods typically increase redundancy to improve repair speed, but this approach results in substantial storage overhead. To enhance repair speed while reducing storage costs, this paper proposes a Machine Learning-based Adaptive Recovery (MLAR) method. Given an application's access patterns for a file, MLAR uses an adaptive encoding model to calculate the optimal code for each file. When applying fault tolerance with the optimal code, lower-redundancy codes can achieve faster repair speeds than higher-redundancy codes. MLAR employs machine learning to predict file access patterns. Experimental results replaying real-world I/O workloads show that, MLAR reduces storage overhead by 12.8% and recovery time by 23.7%, compared to state-of-the-art methods. © 2024 IEEE.

关键词： Redundancy

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Teaching High-Performance Computing in Developing Countries: A Case Study in Mexican Universities 36

Teaching High-Performance Computing in Developing Countries:...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Antonio Trejo-Sanchez, Joel Javier Hernandez-Lopez, Francisco Uh Zapata, Miguel Angel Luis Lopez-Martinez, Jose Fajardo-Delgado, Daniel Cesar Ramirez-Pacheco, Julio CONACYT Ctr Invest Matemat AC Dept Comp Sci Merida Mexico Univ Autonoma Yucatan Dept Comp Sci Merida Mexico Tecnol Nacl Mexico Dept Syst & Computat Ciudad Guzman Mexico Univ Quintana Roo Dept Engn Cancun Mexico

ISBN: (纸本)9781665497473

Teaching High-Performance Computing (HPC) to undergraduate programs represents a significant challenge in most universities in developing countries like Mexico. Deficiencies in the required infrastructure and equipment, inadequate curricula in computer engineering programs (and resistance to change them), students' lack of interest, motivation, or knowledge of this area are the main difficulties to overcome. The COVID-19 pandemic represents an additional challenge to these difficulties in teaching HPC in these programs. Despite the detriments, some strategies have been developed to incorporate the HPC concepts to Mexican students without necessarily modifying the traditional curricula. This paper presents a case study over four public universities in Mexico based on our experience as instructors. We also propose a course that introduces the HPC principles considering the heterogeneous background of the students in such universities. The results are about the number of students enrolling in related classes and participating in extra-curricular projects.

关键词： High-Performance Computing undergraduate program curricula parallel computing

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Near-Field 3D Phase Compensation Method for distributed Radar System based on parallel Implementation Architecture 35

Near-Field 3D Phase Compensation Method for Distributed Rada...

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35th General Assembly and Scientific symposium of the international Union of Radio Science, URSI GASS 2023

作者： Zhang, Zhengyi Su, Jia Tao, Mingliang Fan, Yifei Wang, Ling Northwestern Polytechnical University Xi'an710072 China

ISBN: (纸本)9789463968096

distributed coherent radar system is emerging to improve the radar target detection performance. However, due to the sparse arrangement of distributed radar nodes, the traditional far-field signal processing methods may fail in this scenario. To realize the near-field coherent accumulation, a 3-dimensional (3-D) phase compensation method via GPU device is proposed in this paper. Firstly, according to the geometry of the target and distributed nodes, the near-field target detection model is constructed. Then, the near-field matching function is designed to compensate for the phase difference via 3-D spatial grid search. Considering the high computational complexity of the 3-D search, Graphics processing Unit (GPU) devices are used to realize the parallel acceleration of the proposed method. The experiment results show that the computational speed of near-field target detection is about 2000 times faster than that of the CPU serial method. © 2023 international Union of Radio Science.

关键词： Graphics processing unit

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A scalable adaptive-matrix SPMV for heterogeneous architectures 36

A scalable adaptive-matrix SPMV for heterogeneous architectu...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Tran, Han D. Fernando, Milinda Saurabh, Kumar Ganapathysubramanian, Baskar Kirby, Robert M. Sundar, Hari Univ Utah Salt Lake City UT 84112 USA Univ Texas Austin Austin TX 78712 USA Iowa State Univ Ames IA 50011 USA

ISBN: (纸本)9781665481069

In most computational codes, the core computational kernel is the Sparse Matrix-Vector product (SPMV) that enables specialized linear algebra libraries like PETSc to be used, especially in the distributed memory setting. However, optimizing SPMV performance and scalability at all levels of a modern heterogeneous architecture can be challenging as it is characterized by irregular memory access. This work presents a hybrid approach (HYMV) for evaluating SPMV for matrices arising from PDE discretization schemes such as the finite element method (FEM). The approach enables localized structured memory access that provides improved performance and scalability. Additionally, it simplifies the programmability and portability on different architectures. The developed HYMV approach enables efficient parallelization using MPI, SIMD, OpenMP, and CUDA with minimum programming effort. We present a detailed comparison of HYMV with the two traditional approaches in computational code, matrix-assembled and matrix-free approaches, for structured and unstructured meshes. Our results demonstrate that the HYMV approach achieves excellent scalability and outperforms both approaches, e.g., achieving average speedups of 11x for matrix setup, 1.7x for SPMV with structured meshes, 3.6x for SPMV with unstructured meshes, and 7.5x for GPU SPMV.

关键词： adaptive-matrix matrix-assembled matrix-free element-by-element FEM parallel computing heterogeneous architectures

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Moving from Composable to Programmable 36

Moving from Composable to Programmable

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Chen, Zhongyi Renambot, Luc Long, Lance Brown, Maxine Johnson, Andrew E. Univ Illinois Elect Visualizat Lab Comp Sci Chicago IL 60607 USA

ISBN: (纸本)9781665497473

In today's Big Data era, data scientists require modern workflows to quickly analyze large-scale datasets using complex codes to maintain the rate of scientific progress. These scientists often rely on available campus resources or off-the-shelf computational systems for their applications. Unified infrastructure or over-provisioned servers can quickly become bottlenecks for specific tasks, wasting time and resources. Composable infrastructure helps solve these problems by providing users with new ways to increase resource utilization. Composable infrastructure disaggregates a computer's components - CPU, GPU (accelerators), storage and networking - into fluid pools of resources, but typically relies upon infrastructure engineers to architect individual machines. Infrastructure is either managed with specialized command-line utilities, user interfaces or specification files. These management models are cumbersome and difficult to incorporate into data-science workflows. We developed a high-level software API, Composastructure, which, when integrated into modern workflows, can be used by infrastructure engineers as well as data scientists to reorganize composable resources on demand. Composastructure enables infrastructures to be programmable, secure, persistent and reproducible. Our API composes machines, frees resources, supports multi-rack operations, and includes a Python module for Jupyter Notebooks.

关键词： distributed systems testbed implementation and deployment composable infrastructure deep learning visualization infrastructure as code

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