The proceedings contains 25 papers from the Third international symposium on advanced research in asynchronous circuits and systems. Topics discussed include: pipelines and meshes;asynchronous pipeline control;self-ti...
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The proceedings contains 25 papers from the Third international symposium on advanced research in asynchronous circuits and systems. Topics discussed include: pipelines and meshes;asynchronous pipeline control;self-time meshes;rapid single flux quantum (RSFQ) superconducting circuits;delay-insensitive asynchronouscircuits;CMOS ternary logic;timing analysis;algorithms;extended burst-mode circuits;asynchronous differential equation solver;delay-insensitive algebra;asynchronous dynamic adders;burst mode finite state machines;speed-independent circuits;and asynchronous embedded controller.
The proceedings contain 24 papers. The topics discussed include: a system for asynchronous high-speed chip to chip communication;dynamic logic in four-phase micropipelines;high-performance asynchronous pipeline circui...
ISBN:
(纸本)0818672986
The proceedings contain 24 papers. The topics discussed include: a system for asynchronous high-speed chip to chip communication;dynamic logic in four-phase micropipelines;high-performance asynchronous pipeline circuits;an efficient algorithm for deriving logic functions of asynchronouscircuits;general condition for the decomposition of state holding elements;Fred: an architecture for a self-timed decoupled computer;counterflow pipeline based dynamic instruction scheduling;static scheduling of instructions on micronet-based asynchronous processors;dynamic hazards and speed independent delay model;and some limitations to speed-independence in asynchronouscircuits.
The proceedings contain 19 papers. The topics discussed include: formal verification of safety properties in timed circuits;on directed transformations of delay-insensitive specifications, alternations and dynamic non...
The proceedings contain 19 papers. The topics discussed include: formal verification of safety properties in timed circuits;on directed transformations of delay-insensitive specifications, alternations and dynamic nondeterminism;applying asynchronouscircuits in contactless smart cards;an on-chip dynamically recalibrated delay line for embedded self-timed systems;practical design of globally-asynchronous locally-synchronous systems;CA-BIST for asynchronouscircuits: a case study on the RAPPID asynchronous instruction length decoder;DUDES: a fault abstraction and collapsing framework for asynchronouscircuits;high-level asynchronous system design using the ACK framework;automatic process-oriented control circuit generation for asynchronous high-level synthesis;asynchronous design using commercial HDL synthesis tools;and simple circuits that work for complicated reasons.
The proceedings contain 21 papers. The topics discussed include: verification of delayed-reset domino circuits using ATACS;a timing verifier and timing profiler for asynchronouscircuits;reconfigurable latch controlle...
The proceedings contain 21 papers. The topics discussed include: verification of delayed-reset domino circuits using ATACS;a timing verifier and timing profiler for asynchronouscircuits;reconfigurable latch controllers for low power asynchronouscircuits;behavioral transformations to increase noise immunity in asynchronous specifications;RAPPID: an asynchronous instruction length decoder;memory faults in asynchronous microprocessors;symbolic time separation of events;bounding average time separations of events in stochastic timed Petri nets with choice;timed trace theoretic verification using partial order reduction;projection: a synthesis technique for concurrent systems;a design framework for asynchronous/synchronous circuits based on CHP to HDL translation;from STG to extended-burst-mode machines;analysis and applications of the XDI model;and a self-timed implementation of Boolean functions.
The proceedings contain 23 papers. The topics discussed include: a fast asynchronous Huffman decoder for compressed-code embedded processors;average-case optimized technology mapping of one-hot domino circuits;an asyn...
ISBN:
(纸本)0818683929
The proceedings contain 23 papers. The topics discussed include: a fast asynchronous Huffman decoder for compressed-code embedded processors;average-case optimized technology mapping of one-hot domino circuits;an asynchronous low-power 80C51 microcontroller;predicting performance of micropipelines using Charlie diagrams;accelerating Markovian analysis of asynchronoussystems using string-based state compression;primitive-level pipelining method on delay-insensitive model for RSFQ pulse-driven logic;a FIFO data switch design experiment;ASPRO-216: a standard-cell Q.D.I. 16-bit RISC asynchronous microprocessor;a low-power, low-noise, configurable self-timed DSP;an implicit method for hazard-free two-level logic minimization;average-case optimized transistor-level technology mapping of extended burst-mode circuits;average-case optimized technology mapping of one-hot domino circuits;an asynchronous low-power 80C51 microcontroller;the design of an asynchronous TinyRISC™ TR4101 microprocessor core;asynchronous macrocell interconnect using MARBLE;an asynchronous PRBS error checker for testing high-speed self-clocked serial links;verification of speed-dependences in single-rail handshake circuits;analyzing specifications for delay-insensitive circuits;and a single chip low power asynchronous implementation of an FFT algorithm for space applications.
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