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检索条件"任意字段=International Symposium on Advanced Research in Asynchronous Circuits and Systems"

共 1212 条记录，以下是91-100 订阅

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Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks

Prime Indicants: A Synthesis Method for Indicating Combinati...

引用

15th IEEE international symposium on asynchronous circuits and systems

作者： Toms, W. B. Edwards, D. A. Univ Manchester Sch Comp Sci Manchester M13 9PL Lancs England

ISBN: (纸本)9781424439331

Self-timed circuits present an attractive solution to the problem of process variation. However implementing self-timed combinational logic is complex and expensive. This paper presents a novel method for synthesising indicating implementations of arbitrary encoded function blocks. The synthesis method reduces the cost of the implementations by distributing indication between the individual outputs of a function block. Covers are constructed by determining the minimal cost set of Prime Indicants which are required to indicate all of the input transitions of the function block The results of the procedure are demonstrated on a wide range of combinational logic blocks and show a reduction in literal count of between 38-99%.

关键词： Computer circuits

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High-level asynchronous system design using the ACK framework

High-level asynchronous system design using the ACK framewor...

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6th international symposium on advanced research in asynchronous circuits and systems, ASYNC 2000

作者： Jacobson, Hans Brunvand, Erik Gopalakrishnan, Ganesh Kudva, Prabhakar Department of Computer Science University of Utah United States IBM T.J. Watson Research Center Yorktown Heights NY 10598 United States

Designing asynchronous circuits is becoming easier as a number of design styles are making the transition from research projects to real, usable tools. However, designing asynchronous "systems" is still a difficult problem. We define asynchronous systems to be medium to large digital systems whose descriptions include both datapath and control, that may involve non-trivial interface requirements, and whose control is too large to be synthesized in one large controller. ACK is a framework for designing high-performance asynchronous systems of this type. In ACK we advocate an approach that begins with procedural level descriptions of control and datapath and results in a hybrid system that mixes a variety of hardware implementation styles including burst-mode AFSMs, macromodule circuits, and programmable control. We present our views on what makes asynchronous high level system design different from lower level circuit design, motivate our ACK approach, and demonstrate using an example system design. © 2000 IEEE.

关键词： systems analysis

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A 28nm Configurable asynchronous SNN Accelerator with Energy-Efficient Learning 27

A 28nm Configurable Asynchronous SNN Accelerator with Energy...

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27th IEEE international symposium on asynchronous circuits and systems (ASYNC)

作者： Zhang, Jilin Liang, Mingxuan Wei, Jinsong Wei, Shaojun Chen, Hong Tsinghua Univ Sch Integrated Circuits Beijing Peoples R China Univ Sci & Technol China Sch Microelect Hefei Peoples R China

ISBN: (纸本)9781728141329

In this paper, we put forward an energy-efficient configurable asynchronous SNN accelerator for energy-constrained applications, which includes 256 neurons and 131K synapses with 8-bit fixed point weight. To achieve high energy efficiency and on-chip learning ability, we propose a sparse target propagation (S-TP) algorithm and design the accelerator with Click-based bundled-data asynchronous circuits. The SNN accelerator is implemented in 28nm CMOS process, and the post place and router (post-PAR) simulation results indicate that the SNN accelerator achieves on-chip learning with inference power efficiency of 3.97 pJ/SOP and 95.7% classification accuracy on NMNIST test dataset, which outperforms prior neuromorphic on-chip learning systems.

关键词： asynchronous circuits SNN on-chip learning target propagation algorithm

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High-performance asynchronous pipeline circuits 2

High-performance asynchronous pipeline circuits

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2nd international symposium on advanced research in asynchronous circuits and systems

作者： Yun, KY Beerel, PA Arceo, J UNIV CALIF SAN DIEGO DEPT ECESAN DIEGOCA 92103

ISBN: (纸本)0818672986

This paper presents design and simulation results of two high-performance asynchronous pipeline circuits. The first circuit is a two-phase micropipeline but uses pseudo-static Svensson-style double edge-triggered D-flip-flops (DETDFF) for data storage in place of traditional transmission gate latches or Sutherland's capture-pass latches. The second circuit is a four-phase micropipeline with burst-mode control circuits. We compare our DETDFF and four-phase implementations of a FIFO buffer with the current state-of-the-art micropipeline implementation using four-phase controllers designed by Day and Woods for the AMULET-2 processor. We implemented Day and Woods's design and both of our designs in the MOSIS 1.2 μm CMOS process and simulated them with a 4.6 V power supply and at 100°C. Our SPICE simulations show that our DETDFF and four-phase designs have 70% and 30% higher throughput respectively than Day and Woods's design. This higher throughput for the DETDFF design is due to latching the data on both edges of the latch control, removing the need of a reset phase and simplifying the control structures. Our four-phase design, on the other hand, has higher throughput because of the simplified control structures and the removal of the latch enable buffers from the critical path. The four-phase design, though not quite as fast as the DETDFF design, requires much smaller area for data storage. © 1996 IEEE.

关键词： Timing circuits

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asynchronous, Spatiotemporal Filtering using an Analog Cellular Neural Network Processor 56

Asynchronous, Spatiotemporal Filtering using an Analog Cellu...

引用

56th IEEE international symposium on circuits and systems (ISCAS)

作者： Sengupta, Jonah P. Tomlinson, Michael A. Mendat, Daniel R. Villemur, Martin Andreou, Andreas G. Johns Hopkins Univ Dept Elect & Comp Engn Baltimore MD 21218 USA Silicon Austria Labs Embedded Syst Div Graz Austria

ISBN: (纸本)9781665451093

Neuromorphic processing architectures seek to emulate the functionality of the brain by realizing parallel, efficient, event-based processing which can be directly applied to solve many of the pressing problems within artificial intelligence and big data. However, implementation of these systems leads to slow response times, high power dissipation, or incoherent output. In this paper, an analog cellular neural network processing element is demonstrated to perform asynchronous spatiotemporal filtering operations in an area and power efficient manner. It utilizes a pair of analog memories to encode spike timings and perform event-based bandpass temporal processing. Information from the local clique of temporal filters is leveraged by a parallel, spatial processor which maps CNN arithmetic to the current-domain for compact computation. Preliminary circuit verification demonstrated the ability of the element to perform spatiotemporal filtering operations with latencies less than 1.8 mu s while only consuming 1.6pJ/spike.

关键词： neuromorphic hardware cellular neural network asynchronous processing analog VLSI

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GALS at ETH Zurich: Success or failure ?

GALS at ETH Zurich: Success or failure ?

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12th international symposium on asynchronous circuits and systems

作者： Gurkaynak, Frank K. Oetiker, Stephan Kaeslin, Hubert Felber, Norbert Fichtner, Wolfgang ETH Integrated Syst Lab CH-8092 Zurich Switzerland

ISBN: (纸本)0769524982

The Integrated systems Laboratory (IIS) of ETH Zurich (Swiss Federal Institute of Technology) has been active in Globally-asynchronous Locally-Synchronous (GALS) research since 1998. During this time, a number of GALS circuits have been fabricated and tested successfully on silicon. From a hardware designers point of view, this article summarizes the evolution from proof of concept designs over multi-point interconnects to applications that specifically take advantage of GALS operation to improve cryptographic security. In spite of the fact that they fail to address numerous idiosyncrasies of GALS (such as good partitioning into synchronous islands, port controller design, pausable clock generators, design for test, etc.), hierarchical design flows have been found to form a workable basis. What prevents GALS from gaining a wider acceptance mainly is the initial effort required to come up with a design flow that is efficient and dependable.

关键词： asynchronous machinery

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Low power zero-overhead self-timed division and square root unit combining a single-rail static circuit with a dual-rail dynamic circuit

Low power zero-overhead self-timed division and square root ...

引用

Proceedings of the 1997 3rd international symposium on advanced research asynchronous circuits and systems

作者： Matsubara, Gensoh Ide, Nobuhiro Toshiba Corp Kawasaki Japan

An asynchronous pipeline scheme that combines a low power static circuit with a high-speed dual-rail dynamic circuit is proposed. The scheme utilizes a dual-rail circuit only in the critical path of an SRT division and square root calculation unit. The proposed implementation of the calculation unit reduced power consumption by more than 1/2 of the full-dynamic implementation while maintaining the calculation speed. Because of the elimination of spurious transitions, the proposed implementation showed even less power consumption over synchronous static circuit implementations. By using 0.3 μm triple metal CMOS technology, the calculation time of floating point 56-b full mantissa division and square root is expected to be 45ns in the worst case.

关键词： Combinatorial circuits

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Mitigating asynchronous QDI Drawbacks on MAC Operators with Approximate Multipliers

Mitigating Asynchronous QDI Drawbacks on MAC Operators with ...

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IEEE international symposium on circuits and systems (ISCAS)

作者： Wuerdig, Rodrigo N. Sartori, Marcos L. L. Abreu, Brunno A. Bampi, Sergio Calazans, Ney L. V. Univ Fed Rio Grande do Sul Inst Informat Bento Goncalves Ave 9500 BR-91509900 Porto Alegre Brazil Pontificia Univ Catolica Rio Grande do Sul Sch Technol Ipiranga Ave 6681 BR-90619900 Porto Alegre Brazil

ISBN: (纸本)9781665484855

This work explores the use of asynchronous approximate multiply-accumulate (MAC) operators and research ways to alleviate the inherent area overhead of such circuits, while leveraging on asynchronous circuits advantages. It analyzes three approximate MAC architectures with varying error rates and area trade-offs. Accurate and approximate, synchronous and asynchronous MAC operators are compared. Experiments show it is feasible to decrease the area overhead of the accurate asynchronous MAC from 8.1x down to 1.6x by recurring to approximate multipliers, for varying controlled error rates. The use of asynchronous quasi-delay insensitive (QDI) circuits allows applying extensive voltage scaling to all asynchronous MAC operators. Power and energy per operation can thus be significantly reduced, achieving savings of up to 2.66x in power and 3.17x in energy per operation when compared to the accurate asynchronous MAC.

关键词： Error analysis circuits and systems Voltage asynchronous circuits

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Multiple-Clock Multiple-Edge-Triggered Multiple-Bit Flip-flops for Two-Phase Handshaking asynchronous circuits

Multiple-Clock Multiple-Edge-Triggered Multiple-Bit Flip-flo...

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IEEE international symposium on circuits and systems (ISCAS)

作者： Imai, Masashi Yoneda, Tomohiro Hirosaki Univ Hirosaki Aomori Japan Natl Inst Informat Kunitachi Japan

ISBN: (纸本)9781479934324

This paper proposes multiple-clock multiple-edge-triggered multiple-bit flip-flops for designing simple and straightforward asynchronous control circuits of the two-phase handshaking protocol. The proposed flip-flops have multiple clocks and multiple data inputs, and each data input can be stored in the flip-flop at both the rising edge and the falling edge of the corresponding clock. They can be applied in the asynchronous design of the two-phase handshaking protocol not only for synthesizing simple control circuits, but also for obtaining robust circuits. The performance of the proposed flip-flops have been evaluated using the PTM 22nm HP device parameters.

关键词： Clocks Delays Latches Logic gates MOS devices Protocols Robustness

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asynchronous Containment Control of High-Order Multi-Agent systems With Switching Topologies

Asynchronous Containment Control of High-Order Multi-Agent S...

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IEEE international symposium on circuits and systems (IEEE ISCAS)

作者： Zheng, Wei Xing Shao, Jinliang Shi, Lei Western Sydney Univ Sch Comp Engn & Math Sydney NSW 2751 Australia Univ Elect Sci & Technol China Sch Automat Engn Chengdu 611731 Sichuan Peoples R China

ISBN: (纸本)9781728103976

This paper is concerned with the containment control problem for discrete-time high-order multi-agent systems with switching topologies under the asynchronous setting. Based on the distributed asynchronous consensus protocol using only each agent's own information and its neighbors' partial information, the asynchronous high-order containment control problem with switching topologies is transformed into a product problem of infinite time-varying row-stochastic matrices. Then the properties of row-stochastic matrices are explored to derive a sufficient condition involving graph topologies for asynchronous containment control of high-order multi-agent systems. The theoretical results are finally validated through numerical simulations.

关键词： Multi-agent systems Topology Switches Clocks Stochastic processes Protocols

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