asynchronouscircuits offer promise in handling current and future technology scaling challenges. Unfortunately, their impact has been limited by the lack of design automation. We present A-NTUPLACE, a timing-driven p...
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ISBN:
(纸本)9781479987153
asynchronouscircuits offer promise in handling current and future technology scaling challenges. Unfortunately, their impact has been limited by the lack of design automation. We present A-NTUPLACE, a timing-driven placer uniquely suited to handling quasi delay-insensitive circuits. Our tool uses a generalization of repetitive event rule systems to identify critical signal transitions. The cell placement engine, based on a leading academic placer, NTUPlace3, incorporates net weights to minimize critical wirelengths as well as a novel balancing scheme to ensure isochronic fork constraints are met. We show that our placer is effective at both prioritizing selected nets and balancing forks, demonstrating improvements in 3 of our 4 benchmarks.
AMULET1 demonstrated the feasibility of building an asynchronous implementation of the ARM microprocessor: Although functional, this first asynchronous ARM microprocessor did not fully exploit the potential of the asy...
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ISBN:
(纸本)0818679220
AMULET1 demonstrated the feasibility of building an asynchronous implementation of the ARM microprocessor: Although functional, this first asynchronous ARM microprocessor did not fully exploit the potential of the asynchronous design style to deliver improved performance and power consumption. This paper describes AMULET2e, an embedded system chip incorporating an enhanced asynchronous ARM core (AMULET2), a 4 Kbyte pipelined cache, a flexible memory interface and assorted programmable control functions. AMULET2e silicon demonstrates competitive performance and power-efficiency, ease of design, and innovative features that exploit its asynchronous operation to advantage in power-sensitive applications.
This paper investigates issues which impinge on the design of static instruction schedulers for micronet-based asynchronous processor (MAP) architectures. The micronet model exposes both temporal and spatial concurren...
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This paper presents technology mapping techniques that optimize for average case delay of asynchronous burst-mode control circuits. First, the specification of the circuit is analyzed using stochastic techniques to de...
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This paper presents a technology mapping technique for optimizing the average-case delay of asynchronous combinational circuits implemented using domino logic and one-hot encoded outputs, The technique minimizes the c...
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ISBN:
(纸本)0818683929
This paper presents a technology mapping technique for optimizing the average-case delay of asynchronous combinational circuits implemented using domino logic and one-hot encoded outputs, The technique minimizes the critical path for common input patterns at the possible expense of making less common critical paths longer, To demonstrate the application of this technique, we present a case study of a combinational length decoding block, an integral component of an asynchronous Instruction Length Decoder (AILD) which can be used in Pentium(R) processors, The experimental results demonstrate that the average-case delay of our mapped circuits can be dramatically lower than the worst-case delay of the circuits obtained using conventional worst-case mapping techniques.
A novel asynchronous design method is introduced which combines the area efficiency of bundled data with data dependent computation time. The design of a 16×16 bit multiplier using this technique is explained and...
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A novel asynchronous design method is introduced which combines the area efficiency of bundled data with data dependent computation time. The design of a 16×16 bit multiplier using this technique is explained and evaluated. Simulation results show that area time savings of 20% compared to an equivalent synchronous design can be achieved.
A new method for designing single rail asynchronouscircuits is studied. It utilises additional circuitry to monitor the activity of nodes within combinational logic blocks. When all transitions have halted a completi...
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This paper presents a new methodology to automatically synthesize asynchronouscircuits from descriptions based on process algebra. Traditionally, syntax-directed techniques have been used to generate a netlist of bas...
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Single-track handshake signaling is using the same wire for request and acknowledge signaling. After each 2-phase handshake the wire is back in its initial state. A sequence of three protocol definitions suggests both...
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In this paper the potential speed and power efficiency of two-phase asynchronoussystems operating under a bounded-delay model are explored. It is shown that two-phase bounded-delay systems can significantly outperfor...
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In this paper the potential speed and power efficiency of two-phase asynchronoussystems operating under a bounded-delay model are explored. It is shown that two-phase bounded-delay systems can significantly outperform four-phase approaches published to date. The design of a prototype microprocessor using this two-phase approach is then described, and preliminary results are presented.
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