The realization of Delay-Insensitive (DI) asynchronouscircuits with a CMOS ternary logic is described in this paper. The main advantage of ternary logic is the easy realization of a handshake protocol that significan...
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The realization of Delay-Insensitive (DI) asynchronouscircuits with a CMOS ternary logic is described in this paper. The main advantage of ternary logic is the easy realization of a handshake protocol that significantly reduces the communication requirement, one of the major drawback of asynchronous logic. It is shown how general purpose delay-insensitive circuits are designed with standard ternary logic elements and an original completion detection circuit called watchful. Some elemental circuits (shift-register and adder) are designed and simulated and their performance is compared with other asynchronous solutions, showing that a better performance in term of power consumption has been achieved.
Analog to digital (A-D) converters with a fixed conversion time are subject to errors due to metastability. These errors will occur in all converter designs with a bounded time for decisions, and are potentially sever...
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ISBN:
(纸本)0818683929
Analog to digital (A-D) converters with a fixed conversion time are subject to errors due to metastability. These errors will occur in all converter designs with a bounded time for decisions, and are potentially severe. We estimate the frequency of these errors in a successive approximation converter, and compare the results with asynchronous designs using both a fully speed-independent, and a bundled data approach. It is shown that an asynchronous converter is more reliable than its synchronous counterpart, and that the bundled data design is also faster, on average, than the synchronous design. We also demonstrate trade-offs involved in asynchronous converter designs, such as speed, robustness to delay variations, circuit size and design scalability.
The design of a CMOS standard-cell Quasi-Delay-Insensitive (QDI) 16-bit asynchronous microprocessor is presented. ASPRO-216 is being developed for embedded applications. It is a scalar processor which issues instructi...
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ISBN:
(纸本)0818683929
The design of a CMOS standard-cell Quasi-Delay-Insensitive (QDI) 16-bit asynchronous microprocessor is presented. ASPRO-216 is being developed for embedded applications. It is a scalar processor which issues instructions in-order and completes their execution out-of-order, and it can be customized both at the hardware and software levels to fit specific application requirements. Its architecture extensively uses an overlapping pipelined execution scheme involving desynchronized units. The design flow and circuit style are an original application of A. Martin's method. The expected performance is 200 peak MIPS, 0.5 Watt using a 0.25 mu m technology.
We present the XDI Model for specifying delay-insensitive circuits, that is, reactive systems that correctly exchange signals with their environment in spite of unknown delays incurred by the interface. XDI specificat...
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ISBN:
(纸本)0818683929
We present the XDI Model for specifying delay-insensitive circuits, that is, reactive systems that correctly exchange signals with their environment in spite of unknown delays incurred by the interface. XDI specifications capture restrictions on the communication between circuit and environment, treating both parties equally. They can be visualized as state graphs were each arrow is labeled by a communication terminal and each state by a safety/progress label. We investigate various properties that can be extracted from XDI specifications: automorphisms, environment partitions, autocomparison matrix, and classifications of choice, order dependence, and nondeterminism. We introduce a distinction between static and dynamic output nondeterminism, capturing the difference between design freedom and arbitration. Determining specification properties is useful for validation and design.
Different types of hazards have been studied extensively under the bounded gate and wire delay model. It is well known that under this delay model not all multiple input dynamic logic hazards can be removed from all t...
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This paper proposes a new dynamic instruction scheduler called the asynchronous Fast Dispatch Stack (AFDS). This approach utilizes asynchronous design techniques to implement a dispatch stack-based dynamic instruction...
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This paper presents theory and practical implementation of a method for multi-level logic synthesis of speed-independent circuits. An initial circuit implementation is assumed to satisfy the monotonous cover condition...
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ISBN:
(纸本)0818679220
This paper presents theory and practical implementation of a method for multi-level logic synthesis of speed-independent circuits. An initial circuit implementation is assumed to satisfy the monotonous cover conditions but is technology independent. The proposed method performs both combinational (inserting new gates) and sequential (inserting new memory elements) decomposition of complex gates in a given standard cell library, while preserving original behaviour and speed-independence. The algorithm applies known efficient algebraic factorization techniques from combinational multi-level logic synthesis, but achieves also boolean simplification and sequential decomposition. The method allows sharing of decomposed logic.
This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 mu CMOS process and it shows a power advantage of factor 4 compared to a recent synchronous implementa...
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ISBN:
(纸本)0818683929
This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 mu CMOS process and it shows a power advantage of factor 4 compared to a recent synchronous implementation in the same technology. The chip is fully bit compatible with the synchronous implementation, and timing compatible for external memory access. The circuit is a compiled VLSI-program, using Tangram as VLSI-programming language and the Tangram tool-set to compile the design automatically to a standard-cell netlist. This design approach proves to be powerful enough to describe the microcontroller and derive an efficient implementation. Further, it offers the designer the possibility to explore various alternatives in the design space.
This paper introduces MARBLE, the Manchester asynchronous Bus for Low Energy, a two channel micropipeline bus with centralized arbitration and address decoding which provides for the interconnection of asynchronous VL...
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ISBN:
(纸本)0818683929
This paper introduces MARBLE, the Manchester asynchronous Bus for Low Energy, a two channel micropipeline bus with centralized arbitration and address decoding which provides for the interconnection of asynchronous VLSI macrocells. In addition to basic bus functionality, MARBLE supports bus-bridging and test access, demonstrating that all the functions of a high speed macrocell bus can be implemented efficiently in a fully asynchronous design style. MARBLE is used in the AMULET3i microprocessor to connect the CPU core and DMA controller to RAM, ROM and peripherals. It exploits pipelining of the arbitration, address and data cycles, together with spatial locality optimizations and in-order split transfers, to supply the bandwidth requirements of such a system. The design of a MARBLE initiator data interface used in the AMULET3i is presented, including a Petri-net specification suitable for synthesis using the Petrify tool.
A system for high-speed asynchronous interconnections between VLSI chips is proposed. Communication is performed on three-wire links that have about the same properties as differential interconnections. A bit transmis...
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