Energy optimisation using clustering remains a constant challenge in wireless sensor networks (WSNs). The high volume of data generated within these networks leads to excessive energy consumption when transferring it ...
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The modern-day studies in video surveillance, fireplace detection, face reputation, crowd detection, augmented reality-based totally navigation, and artificial intelligence programs. In video surveillance, deep master...
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The ever-growing complexity of IoT networks ignited by their wide scale adoption in applications such as smart cities, the industrial automation, and health care, compelled to develop sophisticated yet resource effici...
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In this paper, we investigate the benefits of hardware-aware quantization in the gFADES hardware accelerator targeting Graph Convolutional networks (GCNs). GCNs are a type of Graph Neural networks (GNNs) that combine ...
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ISBN:
(纸本)9783031556722;9783031556739
In this paper, we investigate the benefits of hardware-aware quantization in the gFADES hardware accelerator targeting Graph Convolutional networks (GCNs). GCNs are a type of Graph Neural networks (GNNs) that combine sparse and dense data compute requirements that are challenging to meet in resource-constrained embedded hardware. The gFADES architecture is optimized to work with the pruned data representations typically present in graph neural networks for the graph structure and features. It is described in High-Level Synthesis (HLS) which enables efficient design-space exploration of mixed precision hardware configurations. In this work, the mixed-precision design is embedded in the forward pass of the PyTorch back-propagation training loop to enable run-time hardware-aware training. It uses different data types to represent adjacency, feature, weight, internal, and output values which allows for a fine-grained optimization at the tensor level. The resulting hardware configuration after training reduces precision to a 4-bit data type for all inputs. It achieves little to no degradation in the classification accuracy, when training on the Planetoid database dataset, compared to the original 32-bit floating-point. The optimized hardware design running on an AMD/Xilinx Zynq Ultrascale+ FPGA device achieves over 600x speedup compared to the optimized PyTorch software implementation running on the multi-core ARM CPU in the processing system.
This study investigates the resistance of the Home Assistant platform under different types of distributed Denial of Service (DDoS) attacks, namely TCP SYN flood, UDP flood, and ICMP flood, in IPv4 and IPv6 network en...
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This article focuses on communicating and transmitting meaningful parameters between junctions in traffic control systems. Decisions taken at one junction can have a domino effect on subsequent junctions, and good com...
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With the increasing demand for robust security in the rapidly expanding metaverse within 6 G networks, advanced intrusion detection systems (IDS) are becoming essential. This paper introduces a novel hybrid intrusion ...
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The security and dependability of Vehicular Ad-hoc networks (VANETs) are seriously threatened by spoofing attacks. Malicious entities have the ability to undermine the integrity of vehicular communication through the ...
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With the increase in the size of distributedsystems implemented in a global computer environment, mathematical methods for formalizing their development and functioning become one of the important problems. The artic...
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The resource-constrained task scheduling problem has been one of the popular research topics in cloud computing systems. By employing the dynamic voltage and frequency scaling (DVFS) techniques, the task scheduling ca...
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