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IEEE Annual international symposium Virtual Reality

作者： Theophilus Teo Kuniharu Sakurada Maki Sugimoto Keio University Japan

parallel view is a technique that allows a VR user to see multiple locations at a time. It enables the user to control several remote or virtual body parts while seeing parallel views to solve synchronous tasks. However, these techniques only explored the benefits and drawbacks of a user performing different tasks. In this paper, we explored enhancements on a singular or asynchronous task by utilizing information obtained in parallel views. We developed three prototypes where parallel views are fixed, moving in symmetric order, or following the user's eye gaze. We conducted a user study to compare each prototype against traditional VR (without parallel views) in three types of tasks: object search and interaction tasks in a 1) simple environment and 2) complex environment, and 3) object distances estimation task. We found parallel views improved multi-embodiment while each technique helped different tasks. No parallel view provided a clean interface, thus improving spatial presence, mental effort, and user performance. However, participants' feedback highlighted potential usefulness and a lower physical effort by using parallel views to solve complicated tasks.

关键词： Legged locomotion Three-dimensional displays Prototypes Estimation Immersive experience User interfaces Search problems

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HAMBug: A Hybrid CPU-FPGA System to Detect Race Conditions

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2021年第9期68卷 3158-3162页

作者： Almeida, Danilo Damiao Braganca, Lucas Torres, Frank Sill Ferreira, Ricardo Nacif, Jose Augusto M. Univ Fed Vicosa Sci & Technol Inst BR-36570900 Florestal Brazil German Aerosp Ctr Inst Protect Maritime Infrastruct D-27572 Bremerhaven Germany Univ Fed Minas Gerais Grad Program Elect Engn BR-31270901 Belo Horizonte MG Brazil

The evolution of computer algorithms and micro-architectures continuously leads to novel applications and solutions that explore modern computers' potential. A drawback of this development is the rising complexity of hardware-oriented tests during software development. This brief proposes Hambug, a method to support developers during software testing of parallel applications in CPU-FPGA environments. The main component is a run-time memory analyzer that employs shared channels. Thus, Hambug enables memory analysis of parallel applications without influencing the CPU using a hardware-based debug module. Experimental results indicate that this method presents lower slowdown compared with modern dynamic analysis tools.

关键词： Field programmable gate arrays Hardware Random access memory Computer architecture Tools Instruction sets Task analysis parallel computing FPGA heterogeneous architectures software validation

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Polarmask-Tracker: Lightweight Multi-object Tracking and Segmentation Model for Edge Device 19

Polarmask-Tracker: Lightweight Multi-Object Tracking and Seg...

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19th IEEE international symposium on parallel and Distributed Processing with Applications (IEEE ISPA)

作者： Dong, Xiaoyun Ouyang, Zhenchao Guo, Zeling Niu, Jianwei Beihang Univ Hangzhou Innovat Inst Chuanghui Rd 18 Binjiang 310000 Zhejiang Peoples R China Beihang Univ State Key Lab Virtual Real Technol & Syst Xueyuan Rd 37 Beijing 100191 Peoples R China Beihang Univ Sino French Engineer Sch Xueyuan Rd 37 Beijing 100191 Peoples R China

ISBN: (纸本)9781665435741

The image or video input from the camera is one of the important data sources for unmanned vehicles to perceive the environment. However, the 2D/3D bounding box can only provide a very coarse approximation because one box often contains other targets and background. In order to solve the problem of precise target tracking and computing limitations of edge devices, this paper proposes Polarmask-Tracker, a lightweight segmentation-based multi-object tracking network for vehicular edge devices. Polarmask-Tracker extended the lightweight Polarmask segmentation head with tracking vector. The polar mask replaces the traditional mask prediction by regression of a group of fixed edge points in polar coordinate system, which can greatly optimize the computational complexity and regression difficulty of the mask. With an additional tracking vector branch generated based on mask, the model can learn tracking tasks in an end-to-end manner. Finally, we further accelerated the entire model based on TensorRT and achieve real-time tracking on mobile edge computing platform. Different from previous evaluations on the ImageNet and COCO datasets, this study uses the KITTI tracking dataset to extend the instance segmentation task to segmentation tracking, also called MOTS. At the same time, the target scales captured from the autonomous vehicle camera are usually smaller, which also brings additional challenges. Evaluations on NVidia Jetson AGX show that the final Polarmask-Tracker can achieve 122.55 FPS, 46.57 mAP for mask segmentation, 56.418 HOTA for tracking.

关键词： Segmentation tracking deep learning MOTS autonomous vehicle

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An End-to-end Multi-task object Detection using Embedded GPU in Autonomous Driving 22

An End-to-end Multi-task Object Detection using Embedded GPU...

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22nd international symposium on Quality Electronic Design (ISQED)

作者： Zhou, Shanglin Xie, Mimi Jin, Yufang Miao, Fei Ding, Caiwen Univ Connecticut Storrs CT 06269 USA Univ Texas San Antonio San Antonio TX USA

ISBN: (纸本)9781728176413

Autonomous driving has gained popularity due to its high reliability compared to human drivers. Autonomous vehicles combine variety of sensors to perceive their surroundings, and use deep learning (DL) to extract complicated information from the sensing data. However, there are several challenges: Many DL models have explosive model sizes, and therefore not only time consuming but also power consuming when implementing on embedded systems on vehicles, further degrading the battery life-cycle. The current on-board AI treats lane detection and car location separately. In this paper, we propose an end-to-end multi-task environment detection framework. We fuse the 3D point cloud object detection model and lane detection model, with model compression technique applied. As on-board sensors forward information to the multi-task network, it not only parallel two detection tasks to extract combination information, but also reduces entire running time of the DL model. Experiments show by adding the model compression technique, the running speed of multi-task model improves more than 2x. Also, running time of lane detection model on Nvidia Jetson TX2 is almost 6x less comparing with running on CPU, which shows reasonableness of using embedded AI computing device on autonomous vehicle.

关键词： 3D object Detection LIDAR Point Cloud Lane Detection Weight Pruning Embedded computing Device

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A Multi-object Detection Sampling Algorithm For Large Scenes

A Multi-object Detection Sampling Algorithm For Large Scenes

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international symposium on parallel Architectures, Algorithms and Programming (PAAP)

作者： Liang Jin Xiaochuan Li Baoyu Fan Zhenhua Guo Ruidong Li Li Wang Yanwei Wang Yaqian Zhao Rengang Li Inspur Electronic Information Industry Co.Ltd. Jinan China Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co.Ltd. Jinan China

ISBN: (纸本)9781665452199

Multi-object detection in large scenes aims to find objects in images, which usually contain more than one billion pixels. Based on the concept of dividing and conquering, the state-of-the-art (SOTA) methods slice the super-resolution image into patches first and then lower the image solution to detect objects later. The advantage of this method is that it can adapt quickly to regular detection algorithms. However, a set of parameters needs to be set manually, such as the size of sliding windows and overlap, which is quite hard to fit all scenarios. It may result in a loss of samples located at the boundary of the sliding window and the oversampling of inefficient samples that appear within the overlap. In this paper, we propose a object-oriented image sampling algorithm based on anchor boxes during training and multi-scale pyramids during inference. Inspired by the mature object detection baseline Scale-YOLOv4, we present more tricks to fit large scenes. The accuracy can reach 66%, which is 24 points higher than the CascadeRCNN model of the official backbone network ResNet50. Finally, we have won first place in the PANDA object detection tracking using this method.

关键词： Training object oriented modeling Superresolution object detection Programming Image sampling Inference algorithms

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Internet of Things based Cyber-Physical System framework for Real-Time Operations 23

Internet of Things based Cyber-Physical System framework for...

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IEEE 23rd international symposium on Real-Time Distributed computing (ISORC)

作者： Maru, Vatsal Nannapaneni, Saideep Krishnan, Krishna Wichita State Univ Dept Ind Syst & Mfg Engn Wichita KS 67260 USA

ISBN: (纸本)9781728169583

The paper presents an intelligent cyber-physical system (CPS) framework using object detection for real-time operations in an Internet-of-Things (IoT) connected physical environment. To facilitate real-time object detection, we used a variant of Convolutional Neural Network (CNN) known as Faster R-CNN (R stands for the region proposals). The control action related to the detected object is exchanged with the actuation system using Real-Time Data Exchange (RTDE) protocol. We demonstrate the proposed framework to perform pick-and-place operations as it is a widely performed operation on a production floor using a Universal Robot (UR5) as an actuation system.

关键词： Cyber-Physical object Detection Convolutional Neural Network Real-Time Control Universal Robot UR5

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VNEC: A Vectorized Non-Empty Column Format for SpMV on CPUs

VNEC: A Vectorized Non-Empty Column Format for SpMV on CPUs

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Luhan Wang Haipeng Jia Lei Xu Cunyang Wei Kun Li Xianmeng Jiang Yunquan Zhang Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Computer Science and Technology University of Chinese Academy of Sciences Beijing China Microsoft Research

ISBN: (数字)9798350387117

ISBN: (纸本)9798350387124

Sparse matrix-vector multiplication (SpMV) is a widely used computational kernel for many applications. The performance of existing vectorization-oriented and locality-optimized SpMV works is limited by increasing additional memory accesses to the output vector or using expensive gather operations. To address these issues, we present the Vectorized Non-Empty Column (VNEC), a novel SpMV storage format aiming to optimize locality and vectorization while alleviating the existing limitations. The VNEC chunks the sparse matrix by rows and removes the empty columns from each row block to improve input vector locality and reduce extra output vector memory access. It can also relieve the cost of expensive gather operations by padding zeros and employing less costly vector load instruction. Specifically, we design two variants of VNEC for different non-zero distributions and propose an effective heuristic selection model by introducing the Intra-Row Density (IRD) to evaluate which variant is suitable for optimizing a given matrix. Experimental results show that in a multicore environment, VNEC achieves up to 6.94× speedup (2.10× on average) against the standard MKL SpMV routine on the x86 CPU and up to 5.92× speedup (1.73× on average) over ArmPL on the ARM CPU. We emphasize that the VNEC format is practical for real-world iterative applications because of its low preprocessing overhead for format conversion.

关键词： Distributed processing Multicore processing Memory management Graphics processing units Vectors Sparse matrices Iterative methods

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Online Memory Leak Detection in the Cloud-Based Infrastructures 18th

Online Memory Leak Detection in the Cloud-Based Infrastructu...

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18th international Conference on Service-oriented computing (ICSOC)

作者： Jindal, Anshul Staab, Paul Cardoso, Jorge Gerndt, Michael Podolskiy, Vladimir Tech Univ Munich Chair Comp Architecture & Parallel Syst Garching Germany Huawei Munich Res Ctr Huawei Technol Munich Munich Germany

ISBN: (纸本)9783030763527;9783030763510

A memory leak in an application deployed on the cloud can affect the availability and reliability of the application. Therefore, to identify and ultimately resolve it quickly is highly important. However, in the production environment running on the cloud, memory leak detection is a challenge without the knowledge of the application or its internal object allocation details. This paper addresses this challenge of online detection of memory leaks in cloud-based infrastructure without having any internal application knowledge by introducing a novel machine learning based algorithm Precog. This algorithm solely uses one metric i.e. the system's memory utilization on which the application is deployed for the detection of a memory leak. The developed algorithm's accuracy was tested on 60 virtual machines manually labeled memory utilization data provided by our industry partner Huawei Munich Research Center and it was found that the proposed algorithm achieves the accuracy score of 85% with less than half a second prediction time per virtual machine.

关键词： Memory leak Online memory leak detection Memory leak patterns Cloud Linear regression

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Prioritizing Information Flow Violations: Generation of Ranked Security Assertions for Hardware Designs

Prioritizing Information Flow Violations: Generation of Rank...

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IEEE international Workshop on Hardware-oriented Security and Trust (HOST)

作者： Avinash Ayalasomayajula Nusrat Farzana Debjit Pal Farimah Farahmandi University of Florida University of Illinois Chicago

ISBN: (数字)9798350373943

ISBN: (纸本)9798350373950

In today's fast-evolving computing environment, hardware designs like System-on-Chips (SoCs) are ubiquitous due to their small form factor and ability to perform complex operations. These designs often compute using users' private information, necessitating rigorous security checks to prevent vulnerabilities that could expose sensitive data. In this work, we propose a novel approach for assertion generation tailored for checking information leakage in hardware designs. Leveraging static analysis and data mining techniques, we introduce SecMiner, a framework that automatically generates assertions capable of detecting potential information leakages in a hardware design. We develop a novel security label tracking algorithm to help track secure information flows within the design structure whose violation would indicate information leakage. Not all assertions may bear equal security implications; some might be critical in identifying critical vulnerabilities, while others could be simpler in capturing minor concerns. Hence, we introduce a security assertion ranking mechanism that mimics a domain expert to evaluate each assertion based on its relevance to the security of the design and ease of understanding. Our approach uniquely emphasizes identifying information flow within hardware designs, with a detailed and comprehensive ranking mechanism that enhances the depth and breadth of security analysis compared to previous methods. We evaluated our SecMiner framework on open-source hardware benchmarks such as cryptographic and security modules. The experimental results elucidate that our approach is fast, scalable, and computationally efficient with a reasonable memory footprint and can streamline the security validation process by prioritizing high-value assertions.

关键词： Systematics Runtime Recurrent neural networks Static analysis parallel processing Information leakage Hardware

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The AMPERE Project: A Model-driven development framework for highly parallel and EneRgy-Efficient computation supporting multi-criteria optimization 23

The AMPERE Project: A Model-driven development framework for...

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IEEE 23rd international symposium on Real-Time Distributed computing (ISORC)

作者： Quinones, Eduardo Royuela, Sara Scordino, Claudio Gai, Paolo Pinho, Luis Miguel Nogueira, Luis Rollo, Jan Cucinotta, Tommaso Biondi, Alessandro Hamann, Arne Ziegenbein, Dirk Saoud, Hadi Soulat, Romain Forsberg, Bjoern Benini, Luca Mando, Gianluca Rucher, Luigi Barcelona Supercomp Ctr Barcelona Spain Evidence Srl Pisa Italy Inst Super Engn Porto Porto Portugal Sysgo Prague Czech Republic Scuola Super Sant Anna Pisa Italy Bosch Stuttgart Germany Thales Res & Technol Palaiseau France Swiss Fed Inst Technol Zurich Switzerland Thales Italy Florence Italy

ISBN: (纸本)9781728169583

The high-performance requirements needed to implement the most advanced functionalities of current and future Cyber-Physical Systems (CPSs) are challenging the development processes of CPSs. On one side, CPSs rely on model-driven engineering (MDE) to satisfy the non-functional constraints and to ensure a smooth and safe integration of new features. On the other side, the use of complex parallel and heterogeneous embedded processor architectures becomes mandatory to cope with the performance requirements. In this regard, parallel programming models, such as OpenMP or CUDA, are a fundamental brick to fully exploit the performance capabilities of these architectures. However, parallel programming models are not compatible with current MDE approaches, creating a gap between the MDE used to develop CPSs and the parallel programming models supported by novel and future embedded platforms. The AMPERE project will bridge this gap by implementing a novel software architecture for the development of advanced CPSs. To do so, the proposed software architecture will be capable of capturing the definition of the components and communications described in the MDE framework, together with the non-functional properties, and transform it into key parallel constructs present in current parallel models, which may require extensions. These features will allow for making an efficient use of underlying parallel and heterogeneous architectures, while ensuring compliance with non-functional requirements, including those on real-time performance of the system.

关键词： parallel programming models parallel and heterogeneous embedded processor architectures model-driven approaches safety-critical embedded systems

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