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Estimating the Impact of Communication Schemes for distributed Graph Processing 21

Estimating the Impact of Communication Schemes for Distribut...

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21st IEEE international symposium on parallel and distributed Computing (ISPDC)

作者： Ye, Tian Kuppannagari, Sanmukh R. De Rose, Cesar A. F. Wijeratne, Sasindu Kannan, Rajgopal Prasanna, Viktor K. Univ Southern Calif Dept Comp Sci Los Angeles CA 90007 USA Pontificia Univ Catolica Rio Grande do Sul Sch Technol Porto Alegre Brazil

ISBN: (数字)9781665488020

ISBN: (纸本)9781665488020

Extreme scale graph analytics is imperative for several real-world Big Data applications with the underlying graph structure containing millions or billions of vertices and edges. Since such huge graphs cannot fit into the memory of a single computer, distributed processing of the graph is required. Several frameworks have been developed for performing graph processing on distributed systems. The frameworks focus primarily on choosing the right computation model and the partitioning scheme under the assumption that such design choices will automatically reduce the communication overheads. For any computational model and partitioning scheme, communication schemes - the data to be communicated and the virtual interconnection network among the nodes - have significant impact on the performance. To analyze this impact, in this work, we identify widely used communication schemes and estimate their performance. Analyzing the trade-offs between the number of compute nodes and communication costs of various schemes on a distributed platform by brute force experimentation can be prohibitively expensive. Thus, our performance estimation models provide an economic way to perform the analyses given the partitions and the communication scheme as input. We validate our model on a local HPC cluster as well as the cloud hosted NSF Chameleon cluster. Using our estimates as well as the actual measurements, we compare the communication schemes and provide conditions under which one scheme should be preferred over the others.

关键词： distributed Graph Processing Performance Estimation Communication Schemes Cluster Computing

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sNPU: Trusted Execution Environments on Integrated NPUs 51

sNPU: Trusted Execution Environments on Integrated NPUs

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ACM/IEEE 51st Annual international symposium on Computer Architecture (ISCA)

作者： Feng, Erhu Feng, Dahu Du, Dong Xia, Yubin Chen, Haibo Shanghai Jiao Tong Univ Inst Parallel & Distributed Syst SEIEE Shanghai Peoples R China Tsinghua Univ Dept Precis Instrument Beijing Peoples R China Minist Educ Engn Res Ctr Domain Specif Operating Syst Beijing Peoples R China Chinese Acad Sci Key Lab Syst Software Beijing Peoples R China

ISBN: (纸本)9798350326598;9798350326581

Trusted execution environment (TEE) promises strong security guarantee with hardware extensions for security-sensitive tasks. Due to its numerous benefits, TEE has gained widespread adoption, and extended from CPU-only TEEs to FPGA and GPU TEE systems. However, existing TEE systems exhibit inadequate and inefficient support for an emerging (and significant) processing unit, NPU. For instance, commercial TEE systems resort to coarse-grained and static protection approaches for NPUs, resulting in notable performance degradation (10%-20%), limited (or no) multitasking capabilities, and suboptimal resource utilization. In this paper, we present a secure NPU architecture, known as sNPU, which aims to mitigate vulnerabilities inherent to the design of NPU architectures. First, sNPU proposes NPU Guarder to enhance the NPU's access control. Second, sNPU defines new attack surfaces leveraging in-NPU structures like scratchpad and NoC, and designs NPU Isolator to guarantee the isolation of scratchpad and NoC routing. Third, our system introduces a trusted software module called NPU Monitor to minimize the software TCB. Our prototype, evaluated on FPGA, demonstrates that sNPU significantly mitigates the runtime costs associated with security checking (from upto 20% to 0%) while incurring less than 1% resource costs.

关键词： Accelerator Machine learning Security

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GrOUT: Transparent Scale-Out to Overcome UVM's Oversubscription Slowdowns

GrOUT: Transparent Scale-Out to Overcome UVM's Oversubscript...

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1st international Conference on Smart Energy systems and Artificial Intelligence (SESAI)

作者： Lavore, Ian Di Dio Maffi, Davide Arnaboldi, Marco Del Amare, Arnaud Bonetta, Dan Iele Santambrogio, Marco D. Politecn Milan Milan Italy Oracle Labs Zurich Switzerland Vrije Univ Amsterdam Amsterdam Netherlands

ISBN: (纸本)9798350364613;9798350364606

Hardware accelerators have always been difficult to approach. In recent years, we have experienced great efforts to simplify their programming paradigms, especially on CPUs. This led to the development of various domain-specific frameworks and microarchitectural features that facilitated some aspects of this multifaced problem. One such feature is the Unified Virtual Memory (UVM) oversubscription mechanism that allows the developer to handle datasets with a bigger memory footprint than the HW accelerators. Although promising, current UVM faces extreme overheads when running large workloads that reach an oversubscription factor (allocated vs. available memory) ampler than a per-workload threshold. In this work, we propose GrOUT, a language- and domain-agnostic framework that tackles the slowdowns brought by the UVM oversubscription mechanism. In particular, we highlight how a scale-out approach is a feasible solution to solve the slowdowns brought by UVM on workloads from various domains. Moreover, we design a framework capable of autonomously scaling out user-provided workloads, reaching a speedup of more than 24.42x with minimal changes to the application logic.

关键词： GPU distributed systems Unified Virtual Memory Oversubscription Polyglot Programming CUDA

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A HIGHLY parallel FINE-GRAINED SORT-MERGE JOIN ON NEAR MEMORY COMPUTING

A HIGHLY PARALLEL FINE-GRAINED SORT-MERGE JOIN ON NEAR MEMOR...

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IEEE international symposium on Circuits and systems (ISCAS)

作者： Lin, Po-Yen Kuo, Yen-Shi Lai, Bo-Cheng Natl Yang Ming Chiao Tung Univ Hsinchu Taiwan

ISBN: (纸本)9781665484855

In-time processing of database system is imperative to reveal the hidden information. JOIN operation is critical in data analysis, as it occupies almost half of the average execution time in the standard TPC-H benchmark for database processing. In modern databases, transferring data between computing engines and system memory has become one of the main performance challenges. Previous works of Near Memory Computing (NMC) alleviated the costly data transfer, however, the designs still pose inefficiency in terms of processing flow and data management. In this paper, we propose FG-SMJ: a highly parallel fine-grained sort-merge join on near memory computing. The novel data layout allows us to access data from memory chips with fine-grained chip-level parallelism and exploit memory bandwidth. Compared with previous NMC designs, the proposed FG-SMJ attains 3.08x speedup.

关键词： Data analysis Circuits and systems Layout Memory management parallel processing Data transfer DRAM chips

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Integrating parallel, Tensor-Based Computing in Agent-Based Simulators 27

Integrating Parallel, Tensor-Based Computing in Agent-Based ...

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27th IEEE/ACM international symposium on distributed Simulation and Real Time Applications, DS-RT 2023

作者： Sgouros, Nikitas M. University of Piraeus Department of Digital Systems Piraeus Greece

ISBN: (纸本)9798350337846

The rise of deep learning methods has ignited interest in efficient hardware and software systems for tensor-based computing. A question worth investigating is whether other areas in computing can benefit as well from the power and increasing availability of such systems. To this end, we study the integration of tensor-based techniques in agent-based simulators. In particular, we describe methods for the representation as vectors of agent and edge attributes in agent networks and the compilation of rules governing agent behavior and their edge-based interactions into functions that can process and compute such attribute vectors in parallel. We describe a proof of concept implementation of such an idea in Politika, our Elixir-based web framework for concurrent, agent-based simulation. We discuss various simulation scenarios for our implementation and provide directions for future optimizations and integration pathways with concurrent simulation environments. © 2023 IEEE.

关键词： Tensors

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Accelerating MPI Collectives with Process-in-Process-based Multi-object Techniques 23

Accelerating MPI Collectives with Process-in-Process-based M...

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32nd international symposium on High-Performance parallel and distributed Computing (HPDC) part of the ACM Federated Computing Research Conference (FCRC)

作者： Huang, Jiajun Ouyang, Kaiming Zhai, Yujia Liu, Jinyang Si, Min Raffenetti, Ken Zhou, Hui Hori, Atsushi Chen, Zizhong Guo, Yanfei Thakur, Rajeev Univ Calif Riverside Riverside CA 92521 USA NVIDIA Corp Santa Clara CA USA Meta Platforms Inc Menlo Pk CA USA Argonne Natl Lab Argonne IL USA Natl Inst Informat Tokyo Japan

ISBN: (纸本)9798400701559

In the exascale computing era, optimizing MPI collective performance in high-performance computing (HPC) applications is critical. Current algorithms face performance degradation due to system call overhead, page faults, or data-copy latency, affecting HPC applications' efficiency and scalability. To address these issues, we propose PiP-MColl, a Process-in-Process-based Multi-object Interprocess MPI Collective design that maximizes small message MPI collective performance at scale. PiP-MColl features efficient multiple sender and receiver collective algorithms and leverages Process-in-Process shared memory techniques to eliminate unnecessary system call, page fault overhead, and extra data copy, improving intra- and inter-node message rate and throughput. Our design also boosts performance for larger messages, resulting in comprehensive improvement for various message sizes. Experimental results show that PiP-MColl outperforms popular MPI libraries, including OpenMPI, MVAPICH2, and Intel MPI, by up to 4.6X for MPI collectives like MPI_Scatter and MPI_Allgather.

关键词： mpi collective process-in-process distributed systems message passing interface parallel algorithms

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FHNTT: A flexible Number Theoretic Transform design based on hybrid-radix butterfly 22

FHNTT: A flexible Number Theoretic Transform design based on...

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22nd IEEE international symposium on parallel and distributed Processing with Applications, ISPA 2024

作者： Li, Li Li, Rengang Zhao, Yaqian Li, Ruyang Su, Zhiyuan Li, Xuelei Ieit Systems Co. Ltd Jinan China Electronic Information Industry Co. Ltd Beijing China

ISBN: (纸本)9798331509712

Emerging technologies, such as cloud computing and artificial intelligence, significantly arouse concern about data security and privacy. Homomorphic encryption (HE) is a promising invention, which enables computation on encrypted data without decrypting it so as to ensure data security and privacy. Nevertheless, computation within homomorphic encryption involves time-consuming operations, e.g., Number Theoretic Transform (NTT). The tremendous computation overhead is the critical obstacle in deploying HE applications widely. Besides, in order to meet the performance and security requirements of different applications, it is pivotal to design parametric NTT architecture. In this paper, we propose a flexible and parametric NTT accelerating scheme based on hybrid-radix butterfly, named FHNTT. Specifically, we construct high radix butterfly units and divide the computation of them into several stages such that every stage can be performed pipelined. The number of required twiddle factors declines with the increase of radix value. In addition, we adopt address offset strategy to reduce memory consumption. We implement FHNTT on FPGA due to its fine-grained parallel computing capabilities and customized architecture. Empirical results show that FHNTT has an improved performance compared with other NTT architectures and supports a wide range of parameters. Concretely, FHNTT achieves up to 1.99 × to 2.78 × improvement in latency over other FPGA implementations and the memory utilization rate is up to 94%. Moreover, the flexibility makes FHNTT applicable to multiple use cases. © 2024 IEEE.

关键词： FPGA Acceleration Number Theoretic Transform parallel Computing Parametric architecture

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Fuzzy c-Lines for Vertically distributed Database with Missing Values 12

Fuzzy c-Lines for Vertically Distributed Database with Missi...

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Joint 12th international Conference on Soft Computing and Intelligent systems / 23rd international symposium on Advanced Intelligent systems (SCIS and ISIS)

作者： Kunisawa, Kohei Honda, Katsuhiro Ubukata, Seiki Notsu, Akira Osaka Prefecture Univ Grad Sch Engn Sakai Osaka 5998531 Japan Osaka Metropolitan Univ Grad Sch Informat Sakai Osaka 5998531 Japan Osaka Metropolitan Univ Grad Sch Sustainable Syst Sci Sakai Osaka 5998531 Japan

ISBN: (纸本)9781665499248

Privacy preserving data clustering is a useful method for extracting intrinsic cluster structures from distributed databases keeping personal privacy. In a previous research, a model of performing Fuzzy c-Lines clustering was proposed, where a privacy preserving scheme of k-means-type model was adopted with cryptographic calculation. This paper further improves the model for handling incomplete data ignoring the influences of missing values. The element-wise clustering criterion enables to derive local principal component vectors in each data sources by considering minimization of low-rank approximation of observed elements only. Then, fuzzy memberships of each object are calculated in a collaborative manner among organizations, where partial distances between objects and prototypes are derived with cryptographic framework so that intra-organization information is kept secret. The characteristic features of the proposed method are demonstrated through numerical experiments.

关键词： Fuzzy clustering Linear clustering distributed database

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Efficient erasure-coded multi-data block update methods for heterogeneous storage environments 22

Efficient erasure-coded multi-data block update methods for ...

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22nd IEEE international symposium on parallel and distributed Processing with Applications, ISPA 2024

作者： Wang, Hengyu Wei, Bing Luo, Ning Chen, Qian Wu, Yi Zhang, Shudong Zhou, Lijuan Hainan University School of Cyberspace Security Hainan China Hainan University School of International Communication and Arts Hainan China

ISBN: (纸本)9798331509712

Erasure-coded storage systems can achieve highly reliable data storage with low storage overhead. However, updating data blocks necessitates updating parity blocks, and updating multiple data blocks incurs heavy I/O and computational overhead, leading to prolonged update times in heterogeneous storage environments. This paper proposes an erasure-coded multi-data block update method for heterogeneous storage environments, named MBUS, to expedite data updates. MBUS blends re-encoding and delta-based updates and considers factors such as intermediate blocks, computational overhead, and I/O overhead across different storage media. It iteratively computes the minimal I/O time for updating each parity block dynamically. Once the computation equation for each parity block is determined, MBUS prioritizes computing common XOR expressions and reuses the results to reduce the number of XOR operations. MBUS caches a certain number of scheduling plans to minimize redundant computations in subsequent updates, thereby reducing computation time. Experimental results replaying real-world traces demonstrate that MBUS reduces update time by 64.43% compared to state-of-the-art techniques. © 2024 IEEE.

关键词： Computational Optimization Erasure Coding Heterogeneous Storage Environment I/O Optimization Multi-data Block Updates

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Step-Up Current-Source Partial Power Converter for PV systems 13

Step-Up Current-Source Partial Power Converter for PV System...

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13th international symposium on Power Electronics for distributed Generation systems (PEDG)

作者： Abdel-Rahim, Omar Chub, Andrii Blinov, Andrei Vinnikov, Dmitri Hassanpour, Naser Chub, Andrii Tallinn Univ Technol Dept Elect Power Engn & Mechatron Tallinn Estonia Egypt Japan Univ Sci & Technol Alexandria 21934 Egypt

ISBN: (数字)9781665466189

ISBN: (纸本)9781665466189

PV systems are widely used and widely accepted worldwide. Conversion stage efficiency is a critical criterion in selecting PV converters. In order to process PV power in an efficiency way with less cost, this work presents a step-up current source dual active bridge (DAB) partial power converter (PPC) for PV applications. The proposed configuration works as input parallel output series (IPOS) structure, which helps in reducing input current ripple, component size and cost. IPOS structure is convenient for PV application step-up ability, which is common requirements for different PV applications such as grid tied PV applications. The current source dual active bridge (DAB) with its two bidirectional switches and presented modulation allows soft switching of all semiconductors under wide load conditions. Maximum power point Tracking is implemented to track the maximum power of the PV modules by controlling the phase-shift of the converter. This abstract includes the theoretical and simulation analysis, while deep system analysis and more comparative studies will be included in the final version.

关键词： dual active bridge partial power converter input parallel output series

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