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Machine Learning Assisted HPC Workload Trace Generation for Leadership Scale Storage systems 22

Machine Learning Assisted HPC Workload Trace Generation for ...

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31st international symposium on High-Performance parallel and distributed Computing (HPDC)

作者： Paul, Arnab K. Choi, Jong Youl Karimi, Ahmad Maroof Wang, Feiyi Oak Ridge Natl Lab Oak Ridge TN 37830 USA BITS Pilani K K Birla Goa Campus Zuarinagar Goa India

ISBN: (纸本)9781450391993

Monitoring and analyzing a wide range of I/O activities in an HPC cluster is important in maintaining mission-critical performance in a large-scale, multi-user, parallel storage system. Center-wide I/O traces can provide high-level information and fine-grained activities per application or per user running in the system. Studying such large-scale traces can provide helpful insights into the system. It can be used to develop predictive methods for making predictive decisions, adjusting scheduling policies, or providing decisions for the design of next-generation systems. However, sharing real-world I/O traces to expedite such research efforts leaves a few concerns;i) the cost of sharing the large traces is expensive due to this large size, and ii) privacy concern is an issue. We address such issues by building an end-to-end machine learning (ML) workflow that can generate I/O traces for large-scale HPC applications. We leverage ML based feature selection and generative models for I/O trace generation. The generative models are trained on I/O traces collected by the darshan I/O characterization tool over a period of one year. We present a two-step generation process consisting of two deep-learning models, called the feature generator and the trace generator. The combination of two-step generative models provides robustness by reducing the bias of the model and accounting for the stochastic nature of the I/O traces across different runs of an application. We evaluate the performance of the generative models and show that the two-step model can generate time-series I/O traces with less than 20% root mean square error.

关键词： Darshan Generative Modeling Feature Selection Clustering parallel File System

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Integrity Audit Scheme Based on Collaborative Cache in Industrial Internet of Things Environment

Integrity Audit Scheme Based on Collaborative Cache in Indus...

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international symposium on parallel and distributed Processing with Applications, ISPA

作者： Ruizhong Du Ziyuan Wang Yiwei Wang Jiawei Shen Hebei University China

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

Edge caching can provide a limited delay guarantee for delay-sensitive industrial applications. However, in a highly distributed edge environment, cached data is prone to be damaged, and its integrity must be ensured. In this paper, we propose an integrity audit scheme based on collaborative caching in the Industrial Internet of Things (IIoT) environment. This scheme shifts the data storage function from the cloud core network to the edge network, allowing cooperation to fulfill user requests. Firstly, an end-edge-cloud collaborative caching mechanism is designed, partitioning cache space and achieving hierarchical placement through edge collaboration. Secondly, a cache value function combining content recommendation and cost is proposed; cache hit rate and value serve as constraints for replacement and update to dynamically adjust cache data in the edge network. Finally, the analysis proves the correctness and reliability of the scheme. Experimental results show that this scheme can quickly and effectively audit cached data, reduce waiting delay of industrial tasks, and address resource waste from invalid audits.

关键词： Cloud computing distributed processing Collaboration distributed databases Memory User experience Delays Reliability Low latency communication Industrial Internet of Things

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Bandwidth Characterization of DeepSpeed on distributed Large Language Model Training

Bandwidth Characterization of DeepSpeed on Distributed Large...

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2024 IEEE international symposium on Performance Analysis of systems and Software, ISPASS 2024

作者： Hanindhito, Bagus Patel, Bhavesh John, Lizy K. The University of Texas at Austin AustinTX United States Dell Technologies Round RockTX United States

ISBN: (纸本)9798350376388

The exponential growth of the training dataset and the size of the large language model (LLM) significantly outpaces the incremental memory capacity increase in the graphics pro-cessing units (GPUs). Thousands of GPUs are needed to handle state-of-the-art models, which require building an expensive AI GPU cluster that is out of reach for most researchers. This not only makes the cost to train the model more costly but also signifies the environmental impact. To improve the efficiency and scalability of existing infrastructure to handle increasingly demanding training tasks, Microsoft released DeepSpeed, an open-source optimization library for PyTorch that can easily be integrated into existing training flow with minimal code changes. This paper presents a comprehensive third-party evaluation of DeepSpeed for training GPT-2-like LLM on mainstream GPU clusters that are more accessible to everyone. The evaluation includes memory usage analysis and bandwidth characterization in addition to the achieved model size and the attained compute throughput to help compare horizontal and vertical scaling. First, we examine the DeepSpeed ZeRO in single- and dual-node training against the popular distributed training libraries: PyTorch distributed Data-parallel (DDP) with data parallelism and Megatron-LM with data and model parallelism. While DDP achieves higher throughput due to less communication, the model size is limited to a single GPU memory capacity. In single-node training, Megatron-LM can fit a 4x larger model than the DDP, while ZeRO can handle a model with 0.8x-l.2x size of the Megatron-LM. Both Megatron-LM and ZeRO are reasonably competitive in terms of throughput. However, in dual-node training, Megatron- Lmsees a significant drop in throughput due to the excessive inter-node communication, achieving only 25 %-30 % of the throughput offered by ZeRO. Secondly, we evaluate ZeRO-Offload to consolidate multi-node training into single-node. With CPU offloading, ZeRO-Offloa

关键词： Bandwidth

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parallel Data systems With Self-Generating Analytics Demo of self-generating analytics on the hospital supply chain ecosystem

Parallel Data Systems With Self-Generating Analytics Demo of...

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IEEE Region 10 symposium (TENSYMP) - Good Technologies for Creating Future

作者： Baker, Feyaz Chandrasekaran, K. Natl Inst Technol Comp Sci & Engn Dept Surathkal Karnataka India

ISBN: (纸本)9781665400268

We attempt to produce a feasible solution for a real-world problem, using distributed data management concepts. The tool is designed to improve the quality of decision making in hospitals, suppliers, and manufacturers by presenting all information about mutual transactions in a secure and searchable manner. Since the databases of hospitals, suppliers, and manufacturers are large enough that compiling all of them would be difficult, we have applied modified aggregation and query methods for distributed data systems and produce metrics that can support growth. Such a system could help detect outbreaks of disease, produce meaningful data about drug use, and prevent wastage of medical resources.

关键词： distributed data DDM hospital management self-generating analytics

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Combining Static and Dynamic Analysis to Query Characteristics of HPC Applications

Combining Static and Dynamic Analysis to Query Characteristi...

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35th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Welch, Aaron Hernandez, Oscar Chapman, Barbara Univ Houston Houston TX 77004 USA Oak Ridge Natl Lab Oak Ridge TN USA SUNY Stony Brook Stony Brook NY 11794 USA

ISBN: (纸本)9781665435772

Emerging HPC platforms are becoming more difficult to program as a result of systems with different node architectures, some with a small number of "fat" heterogenous nodes (consisting of multiple accelerators) and others with a large number of "thin" homogenous nodes consisting of multi-core CPUs connected with high speed interconnects. New programming models are emerging to address performance portability of the applications as well as a set of scientific libraries that applications can use to exploit these architectures efficiently. To port applications to new architectures, developers need information about their source code characteristics including static and dynamic (e.g. performance) information to refactor the code, understand their data and code structure, and library usage as well as program information to direct their optimisation efforts and make key decisions. In this paper, we describe a tool that combines compiler and profiler information to query program characteristics in a given programming environment. Static and dynamic data about applications is collected and stored together in an SQL database that can be later queried to study application characteristics and patterns. We will demonstrate the capabilities of this tool with an application-driven case study that aims at understanding application code and its use of scientific libraries via a real world example from the molecular simulation application CP2K.

关键词： distributed processing Program processors databases Conferences Tools Programming Libraries

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ISA-Grid: Architecture of Fine-grained Privilege Control for Instructions and Registers 23

ISA-Grid: Architecture of Fine-grained Privilege Control for...

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50th Annual international symposium on Computer Architecture (ISCA)

作者： Fan, Shulin Hua, Zhichao Xia, Yubin Chen, Haibo Zang, Binyu Shanghai Jiao Tong Univ Inst Parallel & Distributed Syst SEIEE Shanghai Peoples R China Minist Educ Engn Res Ctr Domain Specif Operating Syst Shanghai Peoples R China Minist Educ Engn Res Ctr Domain Specif Operating Syst Shanghai AI Lab Shanghai Peoples R China

ISBN: (纸本)9798400700958

Isolation is a critical mechanism for enhancing the security of computer systems. By controlling the access privileges of software and hardware resources, isolation mechanisms can decouple software into multiple isolated components and enforce the principle of least privilege. While existing isolation systems primarily focus on memory isolation, they overlook the isolation of instruction and register resources, which we refer to as ISA (Instruction Set Architecture) resources. However, previous works have shown that exploiting ISA resources can lead to serious security problems, such as breaking the system's memory isolation property by abusing x86's CR3 register. Furthermore, existing hardware only provides privilege-level-based access control for ISA resources, which is too coarse-grained for software decoupling. For example, ARM Cortex A53 has several hundred system instructions/registers, but only four exception levels (EL0 to EL3) are provided. Additionally, more than 100 instructions/registers for system control are available in only EL1 (the kernel mode). To address this problem, this paper proposes ISA-Grid, an architecture of fine-grained privilege control for instructions and registers. ISA-Grid is a hardware extension that enables the creation of multiple ISA domains, with each domain having different privileges to access instructions and registers. The ISA domain can provide bit-level fine-grained privilege control for registers. We implemented prototypes of ISA-Grid based on two different CPU cores: 1) a RISC-V CPU core on an FPGA board and 2) an x86 CPU core on a simulator. We applied ISA-Grid to different cases, including Linux kernel decomposition and enhancing existing security systems, to demonstrate how ISA-Grid can isolate ISA resources and mitigate attacks based on abusing them. The performance evaluation results on both x86 and RISC-V platforms with real-world applications showed that ISA-Grid has negligible runtime overhead (less than 1%).

关键词： Privilege Control Instruction Set Architecture Software Isolation

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Performance Analysis of Array Database systems in Non-Uniform Memory Architecture 29

Performance Analysis of Array Database Systems in Non-Unifor...

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29th Euromicro international Conference on parallel, distributed and Network-Based Processing (PDP)

作者： Dominico, Simone de Almeida, Eduardo C. Alves, Marco A. Z. Meira, Jorge A. Univ Fed Parana Curitiba Parana Brazil Univ Luxembourg Luxembourg Luxembourg

ISBN: (纸本)9781665414555

Array Database Management systems (Array databases) support query processing over multi-dimensional data. Data storage is implemented with non-linear structures to mitigate the shortcomings of the relational model when dealing with raw binary data, such as images, time series, and others. Due In data-hungry nature of nit:In-dimensional data applications. array databases must ideally provide a linear speedup when using a multi-processing system. When dealing with Non-Uniform Memory Access (NUMA) machines, array databases may require massive data movement across the nodes resulting in a severe performance impact. depending on the user operation. In this paper. we analyze the performance impact of the NUMA architecture in the SAVIME and SciDB array databases running five different well-known static thread pinning strategies. Our experiments showed a maximum speedup of these different strategies by 2.49x for SAVIME and up to 1.40 v. fur SciDB. We also observed that these static strategies only yield 48% from the potential speedup (and 26% of the energy reduction), opening a new research topic.

关键词： NUMA Array databases Thread placement

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Avoiding Latencies of Log-Depth parallel Computational Patterns

Avoiding Latencies of Log-Depth Parallel Computational Patte...

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international symposium on parallel and distributed Computing

作者： Mihai Antonescu Mihaela Maliţa Gheorghe M. Ştefan Electronic Devices Circuits and Arch. Dept. Politehnica University of Bucharest Bucharest Romania Computer Science Dept. Rivier University Nashua NH

Above a certain level of complexity, effects appear that reduce the performance of a parallel system. In the context of one-chip parallel computing systems, common parallel patterns can sometimes be expressed as circu...

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Network Adapter for Secure Networks-on-Chip

Network Adapter for Secure Networks-on-Chip

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Julian Haase Nico Volkens Diana Göhringer Chair of Adaptive Dynamic Systems Technische Universität Dresden Germany Centre for Tactile Internet with Human-in-the-Loop (CeTI) Technische Universität Dresden Germany

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

This work explores the security challenges presented by Hardware Trojans (HTs) in Network-on-Chip (NoC) and Multiprocessor System-on-Chip (MPSoC) architectures. It proposes a Network Adapter (NA) approach to mitigate these risks, thereby enhancing the security and reliability of the overall system. The NA uses Authenticated Encryption to maintain confidentiality and ensure packet integrity. In addition, retransmissions recover corrupted or deleted packets, allowing a compromised system with an HT to remain operational. The goal of this paper is to provide insights into the potential benefits and challenges of adding such NA and thus contribute to the development of secure NoC and MPSoCs for future embedded systems.

关键词： distributed processing Embedded systems Conferences Network-on-chip Hardware Encryption Trojan horses

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Runtime Verification for distributed Cyber-Physical systems 40

Runtime Verification for Distributed Cyber-Physical Systems

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40th international symposium on Reliable distributed systems (SRDS)

作者： Momtaz, Anik Michigan State Univ Dept Comp Sci & Engn E Lansing MI 48824 USA

ISBN: (纸本)9781665438193

Cyber-physical systems (CPS) are computer systems with integrated software and physical components that ideally seamlessly interact with the real world and each other. While the use of distributed CPS has rapidly grown over the past decade, so has the need for developing efficient methods to ascertain reliability of these systems by validating their correctness. Since exhaustively validating correctness of a distributed CPS is usually not feasible nor possible, many modern validation methods involve run-time verification of distributed CPS based on safety properties. Our work focuses on developing time and resource efficient assurance techniques that can run in parallel with the execution of these systems to ensure reliability.

关键词： runtime verification reliability distributed cyber-physical systems

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