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检索条件"任意字段=International Symposium on Databases in Parallel and Distributed Systems"

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Paving the way for distributed Non-Blocking Algorithms and Data Structures in the Partitioned Global Address Space model 34

Paving the way for Distributed Non-Blocking Algorithms and D...

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34th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Dewan, Garvit Jenkins, Louis Indian Inst Technol Roorkee Roorkee Uttar Pradesh India Univ Rochester Rochester NY 14627 USA

ISBN: (纸本)9781728174457

The partitioned global address space memory model has bridged the gap between shared and distributed memory, and with this bridge comes the ability to adapt shared memory concepts, such as non-blocking programming, to distributed systems such as supercomputers. To enable non-blocking algorithms, we present ways to perform scalable atomic operations on objects in remote memory via remote direct memory access and pointer compression. As a solution to the problem of concurrent-safe reclamation of memory in a distributed system, we adapt Epoch-Based Memory Reclamation to distributed memory and implement it such that it supports global-view programming. This construct is designed and implemented for the Chapel programming language but can be adapted and generalized to work on other languages and libraries.

关键词： Supercomputers

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Performance comparison of distributed in memory databases in dynamic fog environments

Performance comparison of distributed in memory databases in...

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IEEE international Conference on Big Data and Cloud Computing (BdCloud)

作者： George Vlahavas Anna-Valentini Michailidou Theodoros Toliopoulos Vasileios G. Psomiadis Anastasios Gounaris Athena Vakali School of Informatics Aristotle University of Thessaloniki Thessaloniki Greece

Fog computing is an extension of cloud computing to overcome limitations of the latter. It brings data processing and storage closer to edge devices, while offering higher processing power and storage space compared to the edge. In edge or fog environments, data is often ephemeral, so storing data in memory provides considerable performance benefits. Edge or fog nodes may also fail or disconnect, so distributed database systems are used in order to provide durability and availability. Database performance is an important factor when designing a fog platform. We assess the performance of two distributed, in memory databases, Apache Ignite and Redis, measured as throughput, with respect to different parameters: number of nodes, number of replicas, persistency, network bandwidth, network latency and number of operations. In all cases, Redis outperforms Apache Ignite, however, Apache Ignite scales very well when the number of operations is increased.

关键词： Performance evaluation Degradation Cloud computing distributed databases Bandwidth Benchmark testing Throughput

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GrAPL 2021 Keynote 1: Sparse Adjacency Matrices at the Core of Graph databases: GraphBLAS the Engine Behind RedisGraph Property Graph Database

GrAPL 2021 Keynote 1: Sparse Adjacency Matrices at the Core ...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

Provides an abstract of the keynote presentation and may include a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings.

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Seeds of SEED: Characterizing Enclave-level parallelism in Secure Multicore Processors 1

Seeds of SEED: Characterizing Enclave-level Parallelism in S...

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IEEE international symposium on Secure and Private Execution Environment Design (SEED)

作者： D'Agostino, Brandon Khan, Omer Univ Connecticut Storrs CT 06269 USA

ISBN: (纸本)9781665420259

Secure processor technologies incorporating some form of enclave-based isolation are being deployed in remote cloud computing environments. However, commercial enclave-based systems, such as Intel SGX, incur performance penalties due to architectural limitations arising from enclave interactions with the operating system (OS), encryption and attestation checks for data accesses to main memory, and limitations on the enclave memory size. Enclave software development frameworks like Graphene-SGX aim to improve these limitations with performance enhancements such as exitless calling that offset the latency of expensive enclave interactions with the OS. However, to the best of our knowledge, prior works have not presented a thorough characterization of enclave performance in the presence of increased enclave-level parallelism. In this paper, we characterize how enclave overheads trade off exploitable parallelism on an Intel SGX-enabled multicore CPU for a set of parallelized workloads. We develop a microbenchmark to study the effects of threading as a function of application characteristics, such as the intensity of memory operations and system calls to the OS. We extend our characterization to realistic parallelized enclave workloads from the database and web server domains. We find that application performance scaling with threading is tightly correlated to system call and memory-bound activities in applications. The real world applications stress these constraints, while the underlying system calling implementations deliver competing performance at different thread counts.

关键词： Cloud computing Multicore processing databases Instruction sets Operating systems parallel processing Web servers

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A Status Monitoring Method for Multi-parallel Choppers in Wind Turbine Converters 11

A Status Monitoring Method for Multi-parallel Choppers in Wi...

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IEEE 11th international symposium on Power Electronics for distributed Generation systems (PEDG)

作者： Wu, Rui Parkhou, Masoud Vestas Wind Syst AS Aarhus Denmark

ISBN: (纸本)9781728169903

The multi-parallel chopper system is commonly used in modern MW-level wind turbine converters. Even though the chopper is usually considered as robust and reliable, the semiconductor module can suffer critical junction temperature in extreme fault ride through (FRT) events. This paper proposes a method to monitor and identify if the individual chopper is functioning, degraded, or failed by means of collecting and comparing the parallel semiconductors' temperatures during FRT events. A simulation model is created in PLCES, the accuracy of which is further validated by a dedicated experimental setup including an infrared camera. The proposed method is verified by PLECS simulations.

关键词： DC chopper Insulated Gate Bipolar Transistor (IGBT) fault ride through status monitoring temperature infrared measurement

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Optimizing Huffman Decoding for Error-Bounded Lossy Compression on GPUs

Optimizing Huffman Decoding for Error-Bounded Lossy Compress...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Cody Rivera Sheng Di Jiannan Tian Xiaodong Yu Dingwen Tao Franck Cappello Department of Computer Science University of Alabama Tuscaloosa AL USA Mathematics and Computer Science Division Argonne National LaboratoryLemontILUSA School of Electrical Engineering and Computer Science Washington State University Pullman WA USA School of EECS Washington State University Pullman WA USA

More and more HPC applications require fast and effective compression techniques to handle large volumes of data in storage and transmission. Not only do these applications need to compress the data effectively during simulation, but they also need to perform decompression efficiently for post hoc analysis. SZ is an error-bounded lossy compressor for scientific data, and cuSZ is a version of SZ designed to take advantage of the GPU's power. At present, cuSZ's compression performance has been optimized significantly while its decompression still suffers considerably lower performance because of its sophisticated loss-less compression step-a customized Huffman decoding. In this work, we aim to significantly improve the Huffman decoding performance for cuSZ, thus improving the overall decompression performance in turn. To this end, we first investigate two state-of-the-art GPU Huffman decoders in depth. Then, we propose a deep architectural optimization for both algorithms. Specifically, we take full advantage of CUDA GPU architectures by using shared memory on decoding/writing phases, online tuning the amount of shared memory to use, improving memory access patterns, and reducing warp divergence. Finally, we evaluate our optimized decoders on an Nvidia V100 GPU using eight representative scientific datasets. Our new decoding solution obtains an average speedup of 3.64× over cuSZ's Huffman decoder and improves its overall decompression performance by 2.43× on average.

关键词： distributed processing Analytical models Memory management Graphics processing units distributed databases Throughput Data models

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Fully Dynamic Line Maintenance by Hybrid Programmable Matter

Fully Dynamic Line Maintenance by Hybrid Programmable Matter

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Nooshin Nokhanji Paola Flocchini Nicola Santoro School of Computer Science Carleton University Ottawa Canada School of Electrical Engineering and Computer Science University of Ottawa Ottawa Canada

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

Motivated by the manipulation of nanoscale materials, recent investigations have focused on hybrid systems where passive elements incapable of movement, called tiles, are manipulated by one or more mobile entities, called robots, with limited computational capabilities. Like in most self-organizing systems, the fundamental concern is with the (geometric) shapes created by the position of the tiles; among them, the line is perhaps the most important. The existing investigations have focused on formation of the shape, but not on its reconfiguration following the failure of some of the tiles. In this paper, we study the problem of maintaining a line formation in presence of fully dynamic failures: any tile can stop functioning at any time. We show how this problem can be solved by a group of very simple robots, with the computational power of deterministic finite automata.

关键词： distributed processing Shape Robot kinematics Automata Maintenance engineering System recovery Nanoscale devices

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ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support

ReconOS64: A Hardware Operating System for Modern Platform F...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Lennart Clausing Marco Platzner Department of Computer Science Paderborn University Paderborn Germany

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

Reconfigurable hardware operating systems provide software-like abstractions for hardware accelerators. In particu-lar abstractions that view hardware accelerators as threads and integrate them into a multi-threaded environment have received popularity. However, such abstractions are not yet available for latest platform FPGAs. In this paper, we present ReconOS 64 , a reconfigurable hard-ware operating system for 64-Bit modern platform FPGAs. We discuss the architecture and the build flow and report on a number of experiments that evaluate the performance of the system. In particular, we compare the performance to a previous, 32- Bit ReconOS system. The evaluation shows that the step towards 64- Bit is not only necessary to make hardware operating system support available for modern platform FPGAs, but also improves the performance of operating system calls and memory accesses for hardware threads.

关键词： distributed processing Operating systems Instruction sets Conferences Data transfer Resource management Field programmable gate arrays

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Coloring the Vertices of 9-pt and 27-pt Stencils with Intervals

Coloring the Vertices of 9-pt and 27-pt Stencils with Interv...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Dante Durrman Erik Saule Dept. Mathematics UNC Charlotte Charlotte NC Dept. Computer Science UNC Charlotte Charlotte NC

Graph coloring is commonly used to schedule computations on parallel systems. Given a good estimation of the computational requirement for each task, one can refine the model by adding a weight to each vertex. Instead of coloring each vertex with a single color, the problem is to color each vertex with an interval of colors. In this paper, we are interested in studying this problem for particular classes of graphs, namely stencil graphs. Stencil graphs appear naturally in the parallelisation of applications where the location of an object in a space affects the state of neighboring objects. Rectilinear decompositions of a space generate conflict graphs that are 9-pt stencils for 2D problems and 27-pt stencils for 3D problems. We show that the 5-pt stencil and 7-pt stencil relaxations of the problem can be solved in polynomial time. We prove that the decision problem on 27-pt stencil is NP-Complete. We discuss approximation algorithms with a ratio of 2 for the 9-pt stencil case, and 4 for the 27-pt stencil case. We identify two lower bounds for the problem that are used to design heuristics. We evaluate the effectiveness of several different algorithms experimentally on a set of real instances. Furthermore, these algorithms are integrated into a real application to demonstrate the soundness of the approach.

关键词： Schedules distributed processing Three-dimensional displays Runtime Heuristic algorithms Computational modeling Estimation

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EQC: Ensembled Quantum Computing for Variational Quantum Algorithms 22

EQC: Ensembled Quantum Computing for Variational Quantum Alg...

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49th IEEE/ACM Annual international symposium on Computer Architecture (ISCA)

作者： Stein, Samuel Wiebe, Nathan Ding, Yufei Bo, Peng Kowalski, Karol Baker, Nathan Ang, James Li, Ang Pacific Northwest Natl Lab Richland WA 99354 USA Univ Calif Santa Barbara Santa Barbara CA USA Univ Toronto Toronto ON Canada

ISBN: (纸本)9781450386104

Variational quantum algorithm (VQA), which is comprised of a classical optimizer and a parameterized quantum circuit, emerges as one of the most promising approaches for harvesting the power of quantum computers in the noisy intermediate scale quantum (NISQ) era. However, the deployment of VQAs on contemporary NISQ devices often faces considerable system and time-dependant noise and prohibitively slow training speeds. On the other hand, the expensive supporting resources and infrastructure make quantum computers extremely keen on high utilization. In this paper, we propose a virtualized way of building up a quantum backend for variational quantum algorithms: rather than relying on a single physical device which tends to introduce ever-changing device-specific noise with less reliable performance as time-since-calibration grows, we propose to constitute a quantum ensemble, which dynamically distributes quantum tasks asynchronously across a set of physical devices, and adjusts the ensemble configuration with respect to machine status. In addition to reduced machine-dependant noise, the ensemble can provide significant speedups for VQA training. With this idea, we build a novel VQA training framework called EQC - a distributed gradient-based processor-performance-aware optimization system - that comprises: (i) a system architecture for asynchronous parallel VQA cooperative training;(ii) an analytical model for assessing the quality of a circuit output concerning its architecture, transpilation, and runtime conditions;(iii) a weighting mechanism to adjust the quantum ensemble's computational contribution according to the systems' current performance. Evaluations comprising 500K times' circuit evaluations across 10 IBMQ NISQ devices using a VQE and a QAOA applications demonstrate that EQC can attain error rates very close to the most performant device of the ensemble, while boosting the training speed by 10.5x on average (up to 86x and at least 5.2x). EQC is available at

关键词： Quantum Computing Variational Quantum Algorithms distributed Computing

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