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Methods and Results for Quantum Optimal Pulse Control on Superconducting Qubit systems

Methods and Results for Quantum Optimal Pulse Control on Sup...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Elisha Siddiqui Matekole Yao-Lung Leo Fang Meifeng Lin Computational Science Initiative Brookhaven National Laboratory Upton New York USA

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

The effective use of current Noisy Intermediate-Scale Quantum (NISQ) devices is often limited by the noise which is caused by interaction with the environment and affects the fidelity of quantum gates. In transmon qubit systems, the quantum gate fidelity can be improved by applying control pulses that can minimize the effects of the environmental noise. In this work, we employ physics-guided quantum optimal control strategies to design optimal pulses driving quantum gates on superconducting qubit systems. We test our results by conducting experiments on the IBM quantum hardware using their OpenPulse API. We compare the performance of our pulse-optimized quantum gates against the default quantum gates and show that the optimized pulses improve the fidelity of the quantum gates, in particular the single-qubit gates. We discuss the challenges we encountered in our work and point to possible future improvements.

关键词： distributed processing Working environment noise Conferences Qubit Optimal control Logic gates Superconducting device noise

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SPIDER: An Effective, Efficient and Robust Load Scheduler for Real-time Split Frame Rendering

SPIDER: An Effective, Efficient and Robust Load Scheduler fo...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Bingzheng Ma Ziqiang Zhang Yusen Li Wentong Cai Gang Wang Xiaoguang Liu School of Computer Science Nankai University Tianjin China School of Computer Science and Engineering Nanyang Technological University Singapore

Interactive graphics applications are generally latency-critical, while using multiple GPUs to accelerate such applications becomes possible recently with support from both hardware and software. Split frame rendering (SFR) is a popular approach for multi-GPU rendering, which splits a frame into disjoint regions and assigns the regions to different GPUs. Load scheduling of SFR is a crucial but challenging issue for achieving maximum rendering performance in real-time rendering, which is not well addressed by the existing solutions. In this paper, we propose SPIDER, a load scheduler which leverages fuzzy PID (proportional integral derivative) controller to schedule the rendering workload among GPUs. SPIDER has several distinguished properties: it is a feedback based mechanism which does not need a full knowledge of the dynamic system; it is very computationally efficient and easy to implement; it is highly robust to dynamic workload changes. Extensive experiments are conducted to evaluate SPIDER and the results show that SPIDER always achieves near-optimal performance for various workload patterns, which outperforms the state-of-the-art baselines signif-icantly.

关键词： Graphics Schedules distributed processing Rendering (computer graphics) Real-time systems Software Hardware

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19th IFIP WG 10.3 international Conference on Network and parallel Computing, NPC 2022

19th IFIP WG 10.3 International Conference on Network and Pa...

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19th IFIP WG 10.3 international Conference on Network and parallel Computing, NPC 2022

ISBN: (纸本)9783031213946

The proceedings contain 31 papers. The special focus in this conference is on Network and parallel Computing. The topics include: Adjust: An Online Resource Adjustment Framework for Microservice Programs;cloud-Native Server Consolidation for Energy-Efficient FaaS Deployment;neuProMa: A Toolchain for Mapping Large-Scale Spiking Convolutional Neural Networks onto Neuromorphic Processor;Multi-clusters: An Efficient Design Paradigm of NN Accelerator Architecture Based on FPGA;TrainFlow: A Lightweight, Programmable ML Training Framework via Serverless Paradigm;DRP:Discrete Rank Pruning for Neural Network;transMigrator: A Transformer-Based Predictive Page Migration Mechanism for Heterogeneous Memory;Hardware Acceleration for 1D-CNN Based Real-Time Edge Computing;DLC: An Optimization Framework for Full-State Quantum Simulation;Optimizing Winograd Convolution on GPUs via Partial Kernel Fusion;Approximation Algorithms for Reliability-Aware Maximum VoI on AUV-Aided Data Collections;CCSBD: A Cost Control System Based on Blockchain and DRG Mechanism;Number of UAVs and Mission Completion Time Minimization in Multi-UAV-Enabled IoT Networks;a Spatial-Temporal Similarity-Based Cooperative Surveillance Framework by Edge;A Progressive Transmission Method of Cloud Point Data for HD Map in Autonomous Driving;IMRSim: A Disk Simulator for Interlaced Magnetic Recording Technology;Alleviating Performance Interference Through Intra-Queue I/O Isolation for NVMe-over-Fabrics;WALOR: Workload-Driven Adaptive Layout Optimization of Raft Groups for Heterogeneous distributed Key-Value Stores;Efficient Data Placement for Zoned Namespaces (ZNS) SSDs;SchedP: I/O-aware Job Scheduling in Large-Scale Production HPC systems;adaptive Low-Cost Loop Expansion for Modulo Scheduling;SpacKV: A Pmem-Aware Key-Value Separation Store Based on LSM-Tree;Consistent and Efficient Batch Operations for NoSQL databases with Hybrid Timestamp;SADD: A Novel Systolic Array Accelerator with Dynamic Dataflow for Sparse GEMM i

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AITurbo: Unified Compute Allocation for Partial Predictable Training in Commodity Clusters 21

AITurbo: Unified Compute Allocation for Partial Predictable ...

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30th international symposium on High-Performance parallel and distributed Computing (HPDC)

作者： Zhao, Laiping Li, Fangshu Qu, Wenyu Zhan, Kunlin Zhang, Qingman Tianjin Univ Coll Intelligence & Comp CIC Tianjin Key Lab Adv Networking TANKLAB Tianjin Peoples R China Tianjin Univ TANKLAB CIC Tianjin Peoples R China 58 Com Beijing Peoples R China UNICLOUD Tianjin Peoples R China

ISBN: (纸本)9781450382175

As the scale and complexity of deep learning models continues to grow, model training is becoming an expensive job and only a small number of well-financed organizations can afford. Are the resources in commodity clusters well utilized for training? or how much potential space are still there for further improving the training efficiency in commodity clusters? is an urgent question to answer. In this paper, we review the processing of distributed learning training (DDL) in commodity GPU clusters and find that the current resource utilization is not only low but also imbalanced. We observe two features that can be exploited for further improving the training efficiency: partial predictable training and unified CPU-GPU training. Based on the observations, we present AITurbo, a novel resource scheduler that treats predictable and unpredictable jobs separately, but allocates heterogeneous CPU-GPU resource in a unified way. For predictable jobs, AITurbo designs a predicting model to estimate their performance under various heterogeneous resource allocations. For unpredictable jobs, it schedules them following the least-attained-service-first manner. AITurbo further designs a Borda-count based multi-level feedback queue method to combine them together. AITurbo demonstrates that there is still significant space for improving the training efficiency in commodity clusters. We evaluate AITurbo using jobs from Tensorflow benchmarks, which are submitted following the real trace of three production systems. Experimental results show that, compared with the state-of-the-art, AITurbo can reduce the average job completion time of DDL jobs by 3x.

关键词： Scheduling distributed deep learning partial predictable training heterogeneous resource

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A Study of Graph Analytics for Massive Datasets on distributed Multi-GPUs 34

A Study of Graph Analytics for Massive Datasets on Distribut...

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34th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Jatala, Vishwesh Dathathri, Roshan Gill, Gurbinder Hoang, Loc Nandivada, V. Krishna Pingali, Keshav Univ Texas Austin Austin TX 78712 USA IIT Madras Chennai Tamil Nadu India

ISBN: (纸本)9781728168760

There are relatively few studies of distributed GPU graph analytics systems in the literature and they are limited in scope since they deal with small data-sets, consider only a few applications, and do not consider the interplay between partitioning policies and optimizations for computation and communication. In this paper, we present the first detailed analysis of graph analytics applications for massive real-world datasets on a distributed multi-GPU platform and the first analysis of strong scaling of smaller real-world datasets. We use D-IrGL, the state-of-the-art distributed GPU graph analytical framework, in our study. Our evaluation shows that (1) the Cartesian vertex-cut partitioning policy is critical to scale computation out on GPUs even at a small scale, (2) static load imbalance is a key factor in performance since memory is limited on GPUs, (3) device-host communication is a significant portion of execution time and should be optimized to gain performance, and (4) asynchronous execution is not always better than bulk-synchronous execution.

关键词： Graphics Processing Units Graph Processing distributed systems Performance

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A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA systems

A Message Passing Interface Library for High-Level Synthesis...

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IEEE international symposium on Embedded Multicore Socs (MCSoC)

作者： Kazuei Hironaka Kensuke Iizuka Hideharu Amano Dept. of Information and Computer Science Keio University Yokohama Japan

ISBN: (纸本)9781665465007

One obstacle to application development on multi-FPGA systems with high-level synthesis (HLS) is a lack of support for a programming interface. Implementing and debugging an application on multiple FPGA boards is difficult without a standard interface. Message Passing Interface (MPI) is a standard parallel programming interface commonly used in distributed memory systems. This paper presents a tool-independent MPI library called FiC-MPI that can be used in HLS for multi-FPGA systems in which each FPGA node is connected directly. By using FiC-MPI, various parallel software, including a general-purpose benchmark, can be easily implemented. FiC-MPI was implemented and evaluated on the M-KUBOS cluster consisting of Zynq MPSoC boards connected with a static time-division multiplexing network. By using the FiC-MPI simulator, parallel programs can be debugged before implementing on real machines. As a case study, the Himeno-BMT benchmark was implemented with FiC-MPI. It achieved 178.7 MFLOPS with a single node and scaled to 643.7 MFLOPS with four nodes, and 896.9 MFLOPS with six nodes of the M-KUBOS cluster. Through the implementation, the easiness of developing parallel programs with FiC-MPI on multi-FPGA systems was demonstrated.

关键词： Multiplexing parallel programming Multicore processing Message passing Benchmark testing Libraries Software

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Defending Against Backdoor Attacks with Feature Activation-Based Detection and Model Recovery

Defending Against Backdoor Attacks with Feature Activation-B...

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IEEE international symposium on Network Computing and Applications

作者： Xiao Ma Hong Shen Chan-Tong Lam Faculty of Applied Sciences Macao Polytechnic University Macao SAR China School of Engineering and Technology Central Queensland University Brisbane Australia

ISBN: (数字)9798331510183

ISBN: (纸本)9798331510190

The characteristics of Federated Learning (FL) make FL highly susceptible to malicious poisoning attacks from adversaries. Existing FL defense methods can detect attacks of fixed poisoning patterns, hence are lack of flexibility. Additionally, they typically remove the malicious node models upon detection, leading to a certain degree of data loss. To address these issues, we propose a novel defense method against backdoor attacks in FL systems, effectively enhancing their robustness to malicious poisoning attacks. Specifically, we introduce a malicious update detection method based on feature activation matrices. This method compares the distribution differences of updates from different clients on the same validation data and detects malicious clients based on the outlier rates of their updates. Furthermore, to mitigate the data loss caused by the removal of malicious clients, the server assesses the distance between the distribution of feature activation matrices from the client’s historical updates and the overall model distribution in the current iteration. Based on this distance, the server performs model recovery to a certain extent. Extensive experiments on two benchmark datasets demonstrate that our method accurately detects malicious clients under various state-of-the-art model poisoning attacks. Additionally, the model recovery method provides a notable improvement to the system, ensuring the robustness and performance of the FL system.

关键词： Analytical models Federated learning Computational modeling distributed databases Benchmark testing Feature extraction Data models Robustness Stability analysis Servers

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An Intelligent Test Method of distributed Network Inbreak Based on Cluster Analysis

An Intelligent Test Method of Distributed Network Inbreak Ba...

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Advances in Informatics, Electronics and Education (ISAIEE), international symposium on

作者： Zhang Yunyun Henan College of Industry & Information Technology Jiaozuo China

Due to the lack of large-scale processing of network data in the process of distributed network inbreak intelligent detection, the detection accuracy is low. Therefore, a distributed network inbreak intelligent test method based on cluster analysis is proposed. The distributed network data is preprocessed through data attribute feature transformation, data normalization, data standardization and data dimensionality reduction. According to the preprocessing results, the distributed network data collection is divided into multiple clusters using the fuzzy K-means clustering algorithm., compute the remove from each cluster centre to other data targets, use Euclidean remove to construct the goal function of partition quality, extract distributed network inbreak data, determine the cost function of the convolutional neural networks-gate recurrent unit network model, and use the stochastic gradient descent algorithm to The convolutional neural networks-gate recurrent unit network model is trained, and the extracted distributed network inbreak data is input as an initial sample into the trained convolutional neural networks-gate recurrent unit network model, the model is solved, and the distributed network inbreak intelligent detection results are output. The analysis of the experimental results shows that the proposed method has higher precision and better detection effect in the intelligent detection of distributed network inbreak.

关键词： Neural networks distributed databases Clustering algorithms Stochastic processes Standardization Data models Real-time systems

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An Analysis of Mapping Polybench Kernels to HPC CGRAs

An Analysis of Mapping Polybench Kernels to HPC CGRAs

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Markus Weinhardt Faculty of Engineering and Computer Science Osnabr&#x00FC ck University of Applied Sciences Germany

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

This paper presents a detailed analysis of Mapping the Polybench C 4.2.1 kernels to Coarse-Grain Reconfigurable Arrays (CGRAs), targeting High-Performance Computing (HPC). The results show that the Polybench kernels are well suited for acceleration on a CGRA due to their regular array accesses. However, seperately mapping the innermost loops of the Polybench kernels to a CGRA yields only limited speedups because the small size of the generated dataflow graphs limits the available parallelism and results in a low computational intensity. Therefore, loop transformations which will increase the parallelism and the speedups are suggested. While this work focuses on a specific CGRA and its compiler, the observations and conclusions are also transferable to other CGRAs and their compilers.

关键词： Jacobian matrices Heating systems Finite impulse response filters High performance computing Pipelines Switches parallel processing

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Teaching Heterogeneous Computing Using DPC++

Teaching Heterogeneous Computing Using DPC++

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Joel Fuentes Daniel Ló pez Sebastiá n Gonzá lez Department of Computer Science and Information Technologies Universidad del B&#x00ED o-B&#x00ED o Chill&#x00E1 n Chile

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

The evolution of modern computer systems with conventional processors to complex hardware units with heterogeneous accelerators is a reality. In the last decade, the awareness of teaching parallel computing in undergraduate programs has increased, however, the focus has been mainly on multi-core CPUs. GPUs, FPGAs, and other accelerators are now present in most of the devices people use daily, but their programming is still left to experienced engineers. New high-level programming languages for heterogeneous architectures such as DPC++ represent a good opportunity to bring closer inexperienced programmers to accelerators. In this paper, we present a new Heterogeneous Computing course with a syllabus focused on the foundations of heterogeneous architectures (multi-core CPUs, GPUs, and FPGAs) and their programming with DPC++. We present results from the experience of teaching this course to undergraduate students. Student evaluation and assessment data show that students engaged with the course's learning activities and there is high satisfaction with the contents covered

关键词： distributed processing Education Graphics processing units Computer architecture parallel processing Heterogeneous networks Hardware

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