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Hardware resources analysis of BNNs splitting for FARD-based multi-FPGAs distributed systems 34

Hardware resources analysis of BNNs splitting for FARD-based...

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34th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Fiscaletti, Giorgia Speziali, Marco Stornaiuolo, Luca Santambrogio, Marco D. Sciuto, Donatella Politecn Milan Dipartimento Elettron Informaz & Bioingn DEIB Milan Italy

ISBN: (纸本)9781728174457

FPGAs have proven to be valid architectures to accelerate the inference phase of Convolutional Neural Networks (CNNs). State-of-the-art works also demonstrated that it is possible to take advantage of a distributed FPGA-base system to improve performance, power consumption and scalability of such algorithms. However, the hardware resource usage, communication, and the nodes management become main aspects when dealing with an embedded distributed scenario. In this context, FINN optimizes the FPGA-based CNNs with binarization and FARD is a framework that allows the acceleration of fog computing-based application with FPGAs. In this work, we present how to extend FARD to deal with job-based applications rather than the event-based fog computing scenario. In particular, we analyzed two PYNQ-Z1 connected each other and we implemented a distributed BNN algorithm based on FINN's CnvW2A2. Results show how hardware resources vary according to the division of the network when splitting after each convolutional layer.

关键词： Binarized Neural Networks BNN PYNQ embedded distributed

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FAM-Graph: Graph Analytics on Disaggregated Memory

FAM-Graph: Graph Analytics on Disaggregated Memory

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international symposium on parallel and distributed Processing (IPDPS)

作者： Daniel Zahka Ada Gavrilovska Georgia Institute of Technology

Disaggregated memory is being proposed as a way to provide efficient memory scaling for data intensive applications. High performance interconnect technologies, such as CXL, make disaggregated, fabric-attached-memory (FAM) a viable secondary tier of memory. Previous work on remote memory relies on extending kernel level paging to utilize FAM as an additional storage tier after local memory. These approaches have the advantage of exposing remote memory in application transparent ways that do not require code changes, but they incur large overheads due to the mismatch between the abstraction of a flat virtual address space and the reality of the tiered nature of FAM. In this paper, we present an alternative approach to remote memory based on application-specific objects. We design FAM-Graph - a semi-external graph processing system that leverages application-level properties, such as read only edge data, to efficiently tier data between local and remote memory, and prefetch remote data for local computation. Using several graph algorithms and datasets, we demonstrate that FAM-Graph achieves end-to-end performance within factors of 1–6× of Galois, the state of the art shared memory graph processing system, while using up to 20× less local memory. When Galois is used in conjunction with an OS-level FAM solution, we show that FAM-Graph achieves better end-to-end performance by up to 9× when both systems are configured with the same amount of local memory.

关键词： distributed processing Runtime Costs Prefetching Memory management Software algorithms Semantics

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APDCM 2022 Keynote Talk: Solving QUBOs on Digital and Quantum Computers

APDCM 2022 Keynote Talk: Solving QUBOs on Digital and Quantu...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Thorsten Koch Daniel Rehfeldt Yuji Shinano ZIB

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

Combinatorial Optimization searches for an optimum object in a finite but usually vast collection of objects. This can be used for many practical purposes, like efficient allocation of limited resources, network planning, and hundreds of other applications in almost all fields, e.g., finance, production, scheduling, and inventory control. However, many combinatorial optimization problems are known to be NP-hard, which is often translated simplistically as “intractable.” It is regularly claimed that quantum computers will bring breakthrough progress in solving such challenging combinatorial optimization problems relevant in practice. In particular, Quadratic Unconstraint Binary Optimization (QUBO) problems are said to be the model of choice for use in (adiabatic) quantum systems. We explain some of the meaning and implications, review the state of affairs, and give some computational results to underpin our conclusions.

关键词： Optimization Quantum computing distributed processing Conferences Computers Search problems Resource management

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On the Complexity of Conditional DAG Scheduling in Multiprocessor systems 34

On the Complexity of Conditional DAG Scheduling in Multiproc...

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34th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Marchetti-Spaccamela, Alberto Megow, Nicole Schloeter, Jens Skutella, Martin Stougie, Leen Sapienza Univ Rome Rome Italy INRIA Erable Paris France Univ Bremen Bremen Germany Tech Univ Berlin Berlin Germany Vrije Univ Amsterdam CWI Amsterdam Amsterdam Netherlands

ISBN: (纸本)9781728168760

As parallel processing became ubiquitous in modern computing systems, parallel task models have been proposed to describe the structure of parallel applications. The workflow scheduling problem has been studied extensively over past years, focusing on multiprocessor systems and distributed environments (e.g. grids, clusters). In workflow scheduling, applications are modeled as directed acyclic graphs (DAGs). DAGs have also been introduced in the real-time scheduling community to model the execution of multi-threaded programs on a multi-core architecture. The DAG model assumes, in most cases, a fixed DAG structure capturing only straight-line code. Only recently, more general models have been proposed. In particular, the conditional DAG model allows the presence of control structures such as conditional (if-then-else) constructs. While first algorithmic results have been presented for the conditional DAG model, the complexity of schedulability analysis remains wide open. We perform a thorough analysis on the worst-case makespan (latest completion time) of a conditional DAG task under list scheduling (a.k.a. fixed-priority scheduling). We show several hardness results concerning the complexity of the optimization problem on multiple processors, even if the conditional DAG has a well-nested structure. For general conditional DAG tasks, the problem is intractable even on a single processor. Complementing these negative results, we show that certain practice-relevant DAG structures are very well tractable.

关键词： parallel processing makespan conditional DAG complexity

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ExSAIS: Workshop on Extreme Scaling of AI for Science Message from the workshop chairs

ExSAIS: Workshop on Extreme Scaling of AI for Science Messag...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Svitlana Volkova Robert Rallo

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

ExSAIS: Workshop on Extreme Scaling of AI for Science, brings together researchers in Artificial Intelligence (AI) and High Performance Computing (HPC) to enable scientific discovery at scale. The evolution of machine perception to machine learning and reasoning, and ultimately machine intelligence, has a potential to significantly impact acceleration and advancement of autonomous scientific discovery and the operation of scientific instruments. While machine reasoning will enable intelligent systems to better understand and interact with their physical world, machine intelligence through modeling, simulation and automation, closes the gap between experiments, extreme computing, and scientific discovery. In order to usher in this new era of autonomous science, advances in several areas of artificial intelligence and other disciplines e.g., high-performance computing, data engineering need to come together.

关键词： Conferences Artificial intelligence distributed processing Computational modeling Machine intelligence Instruments High performance computing

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Dynamic Scheduling in distributed Transactional Memory 34

Dynamic Scheduling in Distributed Transactional Memory

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34th IEEE international parallel and distributed Processing symposium (IPDPS)

作者： Busch, Costas Herlihy, Maurice Popovic, Miroslav Sharma, Gokarna Louisiana State Univ Baton Rouge LA 70803 USA Brown Univ Providence RI 02912 USA Univ Novi Sad Novi Sad Serbia Kent State Univ Kent OH 44242 USA

ISBN: (纸本)9781728168760

We investigate scheduling algorithms for distributed transactional memory systems where transactions residing at nodes of a communication graph operate on shared, mobile objects. A transaction requests the objects it needs, executes once those objects have been assembled, and then sends the objects to other waiting transactions. We study scheduling algorithms with provable performance guarantees. Previously, only the offline batch scheduling setting was considered in the literature where transactions and the objects they access are known a priori. Minimizing execution time, even for the offline batch scheduling, is known to be NP-hard for arbitrary communication graphs. In this paper, we analyze for the very first time scheduling algorithms in the online dynamic scheduling setting where transactions and the objects they access are not known a priori and the transactions may arrive online over time. We provide efficient and near-optimal execution time schedules for dynamic scheduling in many specialized network architectures. The core of our technique is a method to convert offline schedules to online. We first describe a centralized scheduler which we then adapt it to a purely distributed scheduler. To our knowledge, these are the first attempts to obtain provably efficient online execution schedules for distributed transactional memory.

关键词： Transactional memory distributed systems execution time data-flow model dynamic scheduling

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A Highly parallel Fine-Grained Sort-Merge Join on Near Memory Computing

A Highly Parallel Fine-Grained Sort-Merge Join on Near Memor...

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IEEE international symposium on Circuits and systems (ISCAS)

作者： Po-Yen Lin Yen-Shi Kuo Bo-Cheng Lai National Yang Ming Chiao Tung University Hsinchu Taiwan

ISBN: (数字)9781665484855

ISBN: (纸本)9781665484862

In-time processing of database system is imperative to reveal the hidden information. JOIN operation is critical in data analysis, as it occupies almost half of the average execution time in the standard TPC-H benchmark for database processing. In modern databases, transferring data between computing engines and system memory has become one of the main performance challenges. Previous works of Near Memory Computing (NMC) alleviated the costly data transfer, however, the designs still pose inefficiency in terms of processing flow and data management. In this paper, we propose FG-SMJ: a highly parallel fine-grained sort-merge join on near memory computing. The novel data layout allows us to access data from memory chips with fine-grained chip-level parallelism and exploit memory bandwidth. Compared with previous NMC designs, the proposed FG-SMJ attains 3.08x speedup.

关键词： Data analysis Circuits and systems Layout Memory management parallel processing Data transfer DRAM chips

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An End-to-end and Adaptive I/O Optimization Tool for Modern HPC Storage systems

An End-to-end and Adaptive I/O Optimization Tool for Modern ...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Bin Yang Yanliang Zou Weiguo Liu Wei Xue School of Software Shandong University National Supercomputing Center Wuxi School of Information Science and Technology ShanghaiTech University Department of Computer Science and Technology Tsinghua University

Real-world large-scale applications expose more and more pressures to storage services of modern supercomputers. Supercomputers have been introducing new storage devices and technologies to meet the performance requirements of various applications, leading to more complicated architectures. High I/O demand of applications and the complicated and shared storage architectures make the issues, such as unbalanced load, I/O interference, system parameter configuration error, and node performance degradation, more frequently observed. And it is challenging to both achieve high I/O performance on application level and efficiently utilize scarce storage resources. We propose AIOT, an end-to-end and adaptive I/O optimization tool for HPC storage systems, which introduces effective I/O performance modeling and several active tuning strategies to improve both the I/O performance of applications and the utilization of storage resources. AIOT provides a global view of the whole storage system and searches for the optimal end-to-end I/O path through flow network modeling. Moreover, AIOT tunes system parameters across multiple layers of the storage system by using the automated identified application I/O behaviors and the instant status of the workload of storage system. We verified the effectiveness of AIOT for balancing I/O load, resolving I/O interference, improving I/O performance by configuring appropriate system parameters, and avoiding I/O performance degradation caused by abnormal nodes through quite a few real-world cases. AIOT has helped to save over ten millions of core-hours during the deployment on Sunway TaihuLight since July 2021. It's worth mentioning that our proposed AIOT is capable of managing other I/O optimization methods across various storage platforms.

关键词： Degradation Performance evaluation distributed processing Adaptive systems Optimization methods Interference Supercomputers

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Data Center Isolated parallel Ring Bus Differential Protection Scheme

Data Center Isolated Parallel Ring Bus Differential Protecti...

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IEEE international symposium on Power Electronics for distributed Generation systems (PEDG)

作者： Taosha Jiang Lisa Qi Yuzhi Zhang Harish Suryanarayana Mohammed Alzamli Harry Handlin Silvio Colombi US Resesarch Center ABB Inc. Raleigh USA Electrification Distribution Solutions ABB Inc. Glendale Heights USA Electrification Smart Power ABB Ltd. Quartino Switzerland

UPSs are used in data centers and other critical power applications for power conditioning and back-up. In addition, to ensure reliability of the data center, a redundant architecture is needed. This increases capital expenses and decreases the utilization rate. One approach is to use the isolated parallel ring bus (IPRB) architecture with static UPS. This features load sharing with active and reactive power transferred through choke inductors to the ring bus. This architecture maximizes the utilization rate while maintaining the reliability of the system. The protection scheme in this IPRB is critical to guarantee the operation in case of any fault. In this paper, the differential protection scheme of the IPRB is explained with simulation and field-testing results. The differential protection can effectively identify and isolate faults to ensure uninterrupted service to the load.

关键词： Power conditioning Fault diagnosis Data centers Reactive power distributed databases distributed power generation Inductors

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Exploiting Reduced Precision for GPU-based Time Series Mining

Exploiting Reduced Precision for GPU-based Time Series Minin...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Yi Ju Amir Raoofy Dai Yang Erwin Laure Martin Schulz Max Plank Computing and Data Facility Technical University of Munich NVIDIA GmbH

The mining of multi-dimensional time series is a crucial step in gaining insights into data obtained from physical systems and from monitoring infrastructures. A widely accepted approach for this challenge is the matrix profile, which, however, is computationally very expensive. It relies on calculating large correlation matrices coupled with sort operations across all dimensions of the data, as well as on performing inclusive scans. All of these steps are inherently data parallel and can, therefore, benefit from execution on GPUs, and even more so from horizontal scaling on multiple GPUs. In addition, the nature of the matrix profile calculation allows the exploitation of reduced precision on GPUs. This offers further improvements to enable the analysis of ever growing data sets in real-world scenarios. Based on these motivations, we introduce the first parallel algorithm for multi-dimensional matrix profile on multiple GPUs exploiting reduced precision modes and provide a highly opti-mized implementation using novel optimization techniques. On one NVIDIA A100 GPU, our implementation achieves a 54x performance improvement in comparison to an optimized single-node execution on a state-of-the-art CPU-based implementation relying on double-precision computation and an additional factor of 1.4x when switching to reduced precision while maintaining sufficient accuracy. We study the accuracy and performance trade-offs for our proposed algorithm in detail and present synthetic and real-world case studies to demonstrate how the reduced precision improves the performance, while accomplishing sufficiently accurate results.

关键词： Time series analysis Layout Graphics processing units Switches Data mining Synchronization parallel algorithms

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