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8th international symposium on parallel architectures, algorithms, and programming, PAAP 2017

ISBN: (纸本)9789811064418

The proceedings contain 57 papers. The special focus in this conference is on parallel architectures, algorithms, and programming . The topics include: Ford motor side-view recognition system based on wavelet entropy and back propagation neural network and levenberg-marquardt algorithm;intrusion detection based on self-adaptive differential evolution extreme learning machine with gaussian kernel;prediction for passenger flow at the airport based on different models;election based pose estimation of moving objects;a novel topology reconfiguration backtracking algorithm for 2d REmesh networks-on-chip;user behaviour authentication model based on stochastic petri net in cloud environment;performance prediction of spark based on the multiple linear regression analysis;exploration of heuristic-based feature selection on classification problems;anti-similarity group shilling attacks;the study of the seabed side-scan acoustic images recognition using bp neural network;node localization of wireless sensor network based on secondary correction error;optimizations of the whole function vectorization based on SIMD characteristics;a stacked denoising autoencoders based collaborative approach for recommender system;research on adaptive canny algorithm based on dual-domain filtering;a dynamic individual recommendation method based on reinforcement learning;research on the pre-distribution model based on seesaw model;an efficient filtration method based on variable-length seeds for sequence alignment;an optimized fusion method for double-wearable-wireless-band platform on cloud-health application;research on concept drift detection for decision tree algorithm in the stream of big data;review of various strategies for gateway discovery mechanisms for integrating internet-MANET.

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11th international symposium on parallel architectures, algorithms and programming, PAAP 2020

11th International Symposium on Parallel Architectures, Algo...

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11th international symposium on parallel architectures, algorithms and programming, PAAP 2020

ISBN: (纸本)9789811600098

The proceedings contain 37 papers. The special focus in this conference is on parallel architectures, algorithms and programming. The topics include: Analysing and Forecasting Electricity Demand and Price Using Deep Learning Model During the COVID-19 Pandemic;cross-database Micro Expression Recognition Based on Apex Frame Optical Flow and Multi-head Self-attention;GPS Intelligent Solution of Aerial Image Target in State Grid EIA Survey;Encryption and Decryption in Conic Curves Cryptosystem Over Finite Field GF(2n) Using Tile Self-assembly;optimizing Embedding-Related Quantum Annealing Parameters for Reducing Hardware Bias;a Behavioural Network Traffic Novelty Detection for the Internet of Things Infrastructures;a Fast Algorithm for Image Segmentation Based on Global Cosine Fitting Energy Model;household Garbage Classification: A Transfer Learning Based Method and a Benchmark;lightweight Neural Network Based Garbage Image Classification Using a Deep Mutual Learning;on the Decycling Problem in a Torus;VBSSR: Variable Bitrate Encoded Video Streaming with Super-Resolution on HPC Education Platform;An Investigation on the Performance of Highly Congested Home WiFi Networks During the COVID-19 Pandemic;using Feed-Forward Network for Fast Arbitrary Style Transfer with Contextual Loss;enhancing Underwater Image Using Multi-scale Generative Adversarial Networks;Inferring Prerequisite Relationships Among Learning Resources for HPC Education;research on Bank Knowledge Transaction Coverage Model Based on Innovation Capacity Analysis;deep Deterministic Policy Gradient Based Resource Allocation in Internet of Vehicles;a Pufferfish Privacy Mechanism for the Trajectory Clustering Task;a Novel Attention Model of Deep Learning in Image Classification;FDRA: Fully Distributed Routing Architecture for Private Virtual Network in Public Cloud.

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Proceedings - 3rd international symposium on parallel architectures, algorithms and programming, PAAP 2010: Message from the PAAP 2010 general co-chairs

Proceedings - 3rd International Symposium on Parallel Archit...

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Proceedings - 3rd international symposium on parallel architectures, algorithms and programming, PAAP 2010 2010年 xi页

作者： Shen, Hong Luo, Zhongxuan

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Proceedings - 3rd international symposium on parallel architectures, algorithms and programming, PAAP 2010: Message from the PAAP 2010 program co-chairs

Proceedings - 3rd International Symposium on Parallel Archit...

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Proceedings - 3rd international symposium on parallel architectures, algorithms and programming, PAAP 2010 2010年 xii页

作者： Zhang, Xianchao Zhong, Cheng Tian, Ye

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Self-Adaptive Micro-Batching for Low-Latency GPU-Accelerated Stream Processing

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international JOURNAL OF parallel programming 2025年第2期53卷 1-24页

作者： Leonarczyk, Ricardo Mencagli, Gabriele Griebler, Dalvan Pontif Catholic Univ Rio Grande Do Sul PUCRS Sch Technol Ave Ipiranga 6681 BR-90619900 Porto Alegre RS Brazil Univ Pisa Comp Sci Dept Largo Bruno Pontecorvo 3 I-56127 Pisa Italy

Stream processing is a computing paradigm enabling the continuous processing of unbounded data streams. Some classes of stream processing applications can greatly benefit from the parallel processing power and affordability offered by GPUs. However, efficient GPU utilization with stream processing applications often requires micro-batching techniques, i.e., the continuous processing of data batches to expose data parallelism opportunities and amortize host-device data transfer overheads. Micro-batching further introduces the challenge of finding suitable micro-batch sizes to maintain low-latency processing under highly dynamic workloads. The research field of self-adaptive software provides different techniques to address such a challenge. Our goal is to assess the performance of six self-adaptive algorithms in meeting latency requirements through micro-batch size adaptation. The algorithms are applied to a GPU-accelerated stream processing benchmark with a highly dynamic workload. Four of the six algorithms have already been evaluated using a smaller workload with the same application. We propose two new algorithms to address the shortcomings detected in the former four. The results demonstrate that a highly dynamic workload is challenging for the evaluated algorithms, as they could not meet the most strict latency requirements for more than 38.5% of the stream data items. Overall, all algorithms performed similarly in meeting the latency requirements. However, one of our proposed algorithms met the requirements for 4% more data items than the best of the previously studied algorithms, demonstrating more effectiveness in highly variable workloads. This effectiveness is particularly evident in segments of the workload with abrupt transitions between low- and high-latency regions, where our proposed algorithms met the requirements for 79% of the data items in those segments, compared to 33% for the best of the earlier algorithms.

关键词： parallel programming Heterogeneous architectures Self-adaptive algorithms GPU programming

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FIPLib: An Image Processing Library for FPGAs Using High-Level Synthesis

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international JOURNAL OF parallel programming 2025年第2期53卷 1-23页

作者： Palazzari, Paolo Faltelli, Marco Iannone, Francesco ENEA CR Casaccia Via Anguillarese 301 I-00123 Rome Italy

This paper investigates the use of High-Level Synthesis (HLS) for designing parallel hardware architectures on FPGAs. HLS compilers, like the one used in Vitis HLS, extract the available parallelism so the HLS languages should be thought as inherently parallel and should be programmed with the target parallel architecture in mind. We discuss how HLS facilitated the development of FIPLib, an image processing library for FPGAs, leveraging the streaming model. This library comprises parallel kernels connected through streams to implement a streaming data-flow computation. Following an overview of the library's functionalities and its parallel implementation, we present the benefits of adopting this FPGA library, particularly in terms of speed and power consumption. We conduct a comparative analysis by implementing two image processing algorithms using both our FPGA library and the equivalent OpenCV CPU and GPU implementation. The results demonstrate that FPGAs programmed through FIPLib can significantly accelerate computations and/or reduce power consumption.

关键词： High-level synthesis parallel processing Image processing FPGA

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POSTER: Minimizing speculation overhead in a parallel recognizer for regular texts 30

POSTER: Minimizing speculation overhead in a parallel recogn...

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30th symposium on Principles and Practice of parallel programming

作者： Borsotti, Angelo Breveglieri, Luca Morzenti, Angelo Reghizzi, Stefano Crespi Politecn Milan Milan Italy CNR IEIIT Milan Italy

ISBN: (纸本)9798400714436

Speculative data-parallel algorithms for language recognition have been widely experimented for various types of finite-state automata (FA), deterministic (DFA) and nondeterministic (NFA), often derived from regular expressions (RE). Such an algorithm cuts the input string into chunks, independently recognizes each chunk in parallel by means of identical FAs, and at last joins the chunk results and checks the overall consistency. In chunk recognition, it is necessary to speculatively start the FAs in any state, thus causing an overhead that reduces the speedup over a serial algorithm. The existing data-parallel DFA-based recognizers suffer from an excessive number of starting states, and the NFA-based ones suffer from the number of nondeterministic transitions. Our data-parallel algorithm is based on the new FA type called reduced-interface DFA (RI-DFA), which minimizes the speculation overhead without incurring in the penalty of nondeterministic transitions or of impractically enlarged DFA machines. The algorithm is theoretically efficient, because it combines the state-reduction of an NFA with the speed of deterministic transitions, thus improving on both DFA-based and NFA-based existing implementations. The practical applicability of the RI-DFA approach is confirmed by a quantitative comparison of the number of starting states for a large public benchmark of complex FAs. On multi-core computing architectures, the RI-DFA recognizer is considerably faster than the NFA-based one on all benchmarks, while it matches the DFA-based one on some benchmarks and performs much better on some others. The extra time needed to construct RI-DFA vs DFA is moderate and is compatible with a practical use. The full paper with all details is in [4]. © 2025 Copyright held by the owner/author(s).

关键词： regular language recognition data-parallel recognition algorithm minimal speculation speedup onmulti-core architecture multi-entry DFA reduced-interface DFA

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24th international Conference on algorithms and architectures for parallel Processing, ICA3PP 2024

24th International Conference on Algorithms and Architecture...

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24th international Conference on algorithms and architectures for parallel Processing, ICA3PP 2024

ISBN: (纸本)9789819615247

The proceedings contain 131 papers. The special focus in this conference is on algorithms and architectures for parallel Processing. The topics include: MARO: Enabling Full MPI Automatic Refactoring in DSL-Based programming Framework;SSC: An SRAM-Based Silence Computing Design for On-chip Memory;TP-BFT: A Faster Asynchronous BFT Consensus with parallel Structure;LTP: A Lightweight On-Chip Temporary Prefetcher for Data-Dependent Memory Accesses;A Neural Network-Based PUF Protection Method Against Machine Learning Attack;Compression Format and Systolic Array Structure Co-design for Accelerating Sparse Matrix Multiplication in DNNs;multidimensional Intrinsic Identity Construction and Dynamic Seamless Authentication Schemes in IoT Environments;invisible Backdoor Attack with Image Contours Triggers;finestra: Multi-aggregator Swarm Learning for Gradient Leakage Defense;DIsFU: Protecting Innocent Clients in Federated Unlearning;multiple-Round Aggregation of Abstract Semantics for Secure Heterogeneous Federated Learning;dynamic Privacy Protection with Large Language Model in Social Networks;a Dynamic Symmetric Searchable Encryption Scheme for Rapid Conjunctive Queries;a Data Watermark Scheme Base on Data Converted Bitmap for Data Trading;distributed Incentive Algorithm for Fine-Grained Offloading in Vehicular Ad Hoc Networks;mitigating Over-Unlearning in Machine Unlearning with Synthetic Data Augmentation;AW-YOLOv9: Adverse Weather Conditions Adaptation for UAV Detection;efficient and Privacy-Preserving Ranking-Based Federated Learning;on-Chain Dynamic Policy Evaluation for Decentralized Access Control;DPG-FairFL: A Dual-Phase GAN-Based Defense Framework Against Image-Based Fairness Data Poisoning Attacks in Federated Learning.

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24th international Conference on algorithms and architectures for parallel Processing, ICA3PP 2024

24th International Conference on Algorithms and Architecture...

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24th international Conference on algorithms and architectures for parallel Processing, ICA3PP 2024

ISBN: (纸本)9789819615278

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24th international Conference on algorithms and architectures for parallel Processing, ICA3PP 2024

24th International Conference on Algorithms and Architecture...

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24th international Conference on algorithms and architectures for parallel Processing, ICA3PP 2024

ISBN: (纸本)9789819615414

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