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检索条件"任意字段=International Symposium on Parallel Architectures, Algorithms, and Programming"

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Multithreaded algorithms for pricing a class of complex options

Multithreaded algorithms for pricing a class of complex opti...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： R.K. Thulasiram L. Litov H. Nojumi C.T. Downing G.R. Gao Department of Computer Science University of Manitoba Winnipeg MAN Canada Stern School of Business New York University New York NY USA Department of Mathematics University of Delaware Newark DE USA Capital Markets Section Division of Research and Statistics Federal Reserve Board Washington D.C. DC USA Department of Elec. & Comp. Engineering University of Delaware Newark DE USA

ISBN: (纸本)0769509908

In this paper, we study multithreaded algorithms for pricing American Style options. We describe the algorithms, explain their relative complexities, and study their performance. The binomial lattice problem has been formulated in two distinct ways. In the first approach, the recursive algorithm, we establish a parent-child relationship between threads while fully exploiting the inherent parallelism. The second approach, the iterative algorithm, follows a data-flow model based on the producer-consumer style of programming. We implement the algorithms on the EARTH platform. The limitations posed by the problem size on the recursive algorithm and the solution to overcome this problem by the iterative algorithm are explained through the performance results. We have then extended these algorithms to study complicated options with dividend paying underlying assets and reported the performance results.

关键词： Pricing Iterative algorithms Earth Yarn Security parallel processing Economic forecasting Delay Instruments Contracts

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Pipeline architecture for DCT/IDCT

Pipeline architecture for DCT/IDCT

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： J. Nikara J. Takola D. Akopian J. Saarinen Digital and Computer Systems Laboratory Tampere University of Technology Tampere Finland Tampereen yliopisto Tampere Pirkanmaa FI Nokia Mobile Phones Tampere Finland

ISBN: (纸本)0780366859

In this paper, a unified sequential architecture for 8-point discrete cosine transform and its inverse is described. The architecture is based on rescheduled constant geometry algorithms, which are mapped onto a one-dimensional structure with the aid of vertical projection. The resulting modular architecture can be efficiently pipelined since arithmetic units are removed from the critical path. In addition, the complexity of the architecture is compared to other previously reported architectures operating over sequential data.

关键词： Discrete cosine transforms Computer architecture Arithmetic parallel processing Signal processing algorithms Throughput Pipeline processing Costs Concurrent computing Geometry

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OVM: Out-of-Order Execution parallel Virtual Machine 01

OVM: Out-of-Order Execution Parallel Virtual Machine

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Proceedings of the 1st international symposium on Cluster Computing and the Grid

作者： George Bosilca Gilles Fedak F Cappello

ISBN: (纸本)9780769510101

High performance computing on parallel architectures currently uses different approaches depending on the hardware memory model of the architecture, the abstraction level of the programming environment and the nature of the application. In this paper, we introduce an original client-server execution model based on RPCs called Out-of-order parallel Virtual Machine (OVM). OVM aims to provide three main features: portability through a unique memory model, load-balancing using a plug-in support and high performance provided by several optimizations. The main optimizations are: non-blocking RPCs, data flow management, persistent and non persistent data, static data set distribution, dynamic scheduling and asynchronous global operations. We present OVM general architecture and demonstrate high performance for regular parallel applications, a parallel application with load balancing needs and a real time parallel application.

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Data locality exploitation in algorithms including sparse communications

Data locality exploitation in algorithms including sparse co...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： G. Bandera E.L. Zapata Computer Architecture Department University of Malaga Malaga Spain

ISBN: (纸本)0769509908

Complexity in real codes is sometimes due to the utilization of multi-vector data structures, but there are not many compile-time approaches dealing with this problem, Moreover current compilation techniques only analyze single vectors. This paper describes how the performance can be improved if semantical bindings are taken into account during the parallelization. Our approach is a first step to converge from the data-parallel paradigm to the automatic parallelization, by reducing the number of directives on code. We apply a multi-loop analysis and a sparse privatization to replace the owner computes rule. Additionally, our support will be able to parallelize loops with some of levels of indirections on a left-hand side. In this paper, we also present three alternatives to store the sending information, and two algorithms to calculate coordinates from pointers. Both issues have a critical importance when the parallelized algorithm requires a sparse communication.

关键词： Sparse matrices Data structures parallel programming Performance analysis Algorithm design and analysis Computer architecture Privatization Concurrent computing Program processors Educational programs

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PAWS: collective interactions and data transfers

PAWS: collective interactions and data transfers

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international symposium on High Performance Distributed Computing

作者： K. Keahey P. Fasel S. Mniszewski Argonne National Laboratory Argonne IL USA Los Alamos National Laboratories Los Alamos NM USA

The authors discuss problems and solutions pertaining to the interaction of components representing parallel applications. We introduce the notion of a collective port which is an extension of the Common Component Architecture (CCA) ports and allows collective components representing parallel applications to interact as one entity. We further describe a class of translation components, which translate between the distributed data format used by one parallel implementation to that used by another. A well known example of such components is the MxN component which translates between data distributed on M processors to data distributed on N processors. We describe its implementation in parallel Application Work Space (PAWS), as well as the data structures PAWS uses to support it. We also present a mechanism allowing the framework to invoke this component on the programmer's behalf whenever such translation is necessary, freeing the programmer from treating collective component interactions as a special case. In doing that, we introduce framework-based, user-defined distributed type casts. Finally, we discuss our initial experiments in building optimized complex translation components out of atomic functionalities.

关键词： Plasma welding Laboratories programming profession Data structures Packaging Timing Shape Component architectures US Government Protection

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An automatic scheduler for real-time vision applications

An automatic scheduler for real-time vision applications

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Mau-Tsuen Yang R. Kasturi A. Sivasubramaniam Computer Science and Information Engineering National Dong Hwa University Taiwan Computer Science and Engineering Pennsylvania State University USA

ISBN: (纸本)0769509908

Many computes vision applications are computationally challenging especially when they need to meet real-time constraints. A major problem with special purpose systems is that they require the developers of image-processing applications to be aware of the low-level hardware design, making the task cumbersome. To avoid inflexible and expensive hardware designs, another possible alternative is a network of workstations (NOW) platform put together with off-the-shelf workstations and networking hardware. Still, one had to manually schedule an algorithm to the available processors of the NOW to make efficient use of the resources. However, this approach is time consuming and impractical for a vision system that must perform a variety of different algorithms, with new algorithms being constantly developed. Improved support for program development is absolutely necessary before the full benefits of parallel architectures can be realized for vision applications. Towards this goal, an automatic compile-time scheduler has been developed to schedule input tasks of vision applications with precedence constraints onto available processors. The scheduler exploits both spatial (parallelism) and temporal (pipelining) concurrency to make the best use of machine resources. Two important scheduling problems are addressed. First, given a task graph and a desired throughput, a schedule is constructed to achieve the desired throughput with the minimum number of processors. Second, given a task graph and a finite set of available resources, a schedule is constructed such that the throughput is maximized while meeting the resource constraints. Results from simulations show that the scheduler and proposed optimization techniques effectively tackle these problems by maximizing the processor utilization. A code generator has been developed to generate parallel programs automatically. The execution profiles of the resulting parallel programs demonstrate the feasibility of the scheduler. The to

关键词： Processor scheduling Hardware Throughput Computer applications Computer vision Workstations Scheduling algorithm Machine vision parallel architectures parallel processing

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parallel retrograde analysis on different architecture

Parallel retrograde analysis on different architecture

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international symposium on High Performance Distributed Computing

作者： Ren Wu D.F. Beal HP Laboratories Hewlett Packard Company USA Department of Computer Science Queen Mary & Westfield College London University UK

Retrograde analysis is an efficient exhaustive search method. It is a powerful tool that can be used in solving problems where end states have known values but starting states do not. It has been widely used to solve mathematically-precise games such as chess endgames, and is potentially usable in energy-minimization problems. With increasing computing power, both in speed and storage capacity, retrograde analysis will become more and more useful. This paper looks at successful applications to games, the challenges ahead and the modifications that are required to utilize distributed hardware. The power and the usefulness of retrograde analysis are still limited by the computing resources one has access to. Today, the best sequential retrograde algorithms are capable of solving problems with about 10/sup 9/ states in a few hours on a standard personal computer. Bigger problems need more powerful computers, or take much longer to solve, or are simply out of the reach of today's technologies. Introducing parallelism to retrograde analysis is a natural way to attack the bigger problems. There are today three main architectures available for doing parallel retrograde analysis, namely symmetric multiprocessor (SMP) systems, high-speed network-based distributed systems and Internet-based distributed systems. In this paper, we discuss some of the key issues in doing parallel retrograde analysis on these different architectures. Technical challenges are addressed in detail, as well as some examples and proposals. These examples and proposals are drawn from various board games, but the ideas can be applied to other problem domains.

关键词： Computer architecture Proposals Laboratories Search methods Hardware Microcomputers parallel processing Multiprocessing systems High-speed networks IP networks

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Asynchronous resource management

Asynchronous resource management

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international symposium on parallel and Distributed Processing (IPDPS)

作者： S. Vajracharya D.G. Chavarria-Miranda Los Alamos National Laboratory Los Alamos NM USA Rice University Houston TX USA

ISBN: (纸本)0769509908

As the organization of high-performance computers becomes more complex, the task of managing resources on them becomes increasingly difficult. The software layers which include the operating system, the runtime system, and the compiler must now map applications to machine architectures that consist of multiple CPUs, several layers of cache, deep memory hierarchies, file systems, interconnects, network interface cards, along the logical resources defined in the software system. To fully utilize all the available resources, software systems may use multiple sequential processes or threads that act on the passive resources of the system. This paper introduces a resource-centric event-driven model, where resources are active objects. We describe an algorithm that implements this model and show that this can significantly improve the performance of a wide variety of applications.

关键词： Resource management Streaming media Software systems Yarn Concurrent computing programming profession Delay Application software Network interfaces Computer aided instruction

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Novel semiconductor device approach for finding acceptable solutions to classes of graph-based computing problems not otherwise possible

Novel semiconductor device approach for finding acceptable s...

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international symposium Semiconductor Device Research (ISDRS)

作者： N. DeClaris A.A. Iliadis A. Lacaze Electrical and Computer Engineering Department University of Maryland Baltimore MD USA Electrical and Computer Engineering Department University of Maryland College Park MD USA

ISBN: (纸本)0780374320

The paper begins with an overview of graph-based concepts and formulations that make it possible to find computational solutions to very complex problems, based on current digital semiconductor devices. Problems classes, of ever-increasing complexity, national and global scope, characterized by massively parallel and distributed graph-based architectures, are discussed as well as the etiology of the inability of current digital-microprocessor-based computing schemes to addressed them. Next the framework of a graph-based approach is outlined for conceptualizing, designing and implementing novel semiconductor devices for new information-processing schemes that make it possible to find acceptable solutions in real time. The paper concludes with illustrative examples from an ongoing design and implementation effort.

关键词： Semiconductor devices Hardware Computer architecture Concurrent computing Distributed computing Information processing parallel processing Educational institutions Software algorithms Physics computing

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Variable partitioning for dual memory bank DSPs

Variable partitioning for dual memory bank DSPs

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international Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： R. Leupers D. Kotte Department of Computer Science 12 University of Dortmund Dortmund Germany

DSPs with dual memory banks offer high memory bandwidth, which is required for high-performance applications. However, such DSP architectures pose problems for C compilers, which are mostly not capable of partitioning program variables between memory banks. As a consequence, time-consuming assembly programming is required for an efficient coding of time-critical algorithms. This paper presents a new technique for automatic variable partitioning between memory banks in compilers, which leads to a higher utilization of available memory bandwidth in the generated machine code. We present experimental results obtained by integrating the proposed technique into an existing C compiler for the AMS Gepard, an industrial DSP core.

关键词： Digital signal processing Bandwidth Assembly Program processors parallel processing Computer science Application software Computer architecture Time factors Partitioning algorithms

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