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检索条件"任意字段=International Symposium on Parallel Architectures, Algorithms, and Programming"

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Compiler optimization of implicit reductions for distributed memory multiprocessors

Compiler optimization of implicit reductions for distributed...

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international symposium on parallel Processing

作者： B. Lu J. Mellor-Crummey Department of Computer Science Rice University USA

This paper presents reduction recognition and parallel code generation strategies for distributed-memory multiprocessors. We describe techniques to recognize a broad range of implicit reduction operations, including those involving statements at multiple loop nesting levels and intermixed with conditional control flow. We introduce two new optimizations: factoring which increases data locality for SUM and PRODUCT reductions, and index encoding which enables a single global communication to accomplish both an extreme value reduction and an extreme value location reduction. We have implemented these techniques in the dHPF compiler for High Performance Fortran (HPF). We evaluate their effectiveness experimentally by compiling several reduction benchmarks with dHPF and two commercial HPF compilers, and comparing the performance of the generated code on an IBM SP2. Our results show that our recognition techniques are more powerful and that our index encoding and factoring optimizations can improve performance by a factor of two where they apply.

关键词： Optimizing compilers Concurrent computing Program processors Iterative algorithms Computer science Identity-based encryption Encoding Global communication Image coding parallel programming

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Using algebraic transformations to optimize expression evaluation in scientific code 98

Using algebraic transformations to optimize expression evalu...

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international Conference on parallel Architecture and Compilation Techniques (PACT)

作者： J. Zory F. Coelho Centre de Recherche en Informatique École Nationale Supérieure des Mines de Paris Fontainebleau France

ISBN: (纸本)9780818685910

Algebraic properties such as associativity or distributivity allow the manipulation of a set of mathematically equivalent expressions. However as shown in this paper the cost of evaluating such expressions on a computer is not constant within this domain. We suggest the use of algebraic transformations to improve the performance of computationally intensive applications on modern computer architectures. We claim that taking into account instruction-level parallelism and the new capabilities of processors when applying these transformations leads to large run-time improvements. Due to a combinatorial explosion, associative commutative pattern-matching techniques cannot systematically be used in this context. Thus, we introduce two performance enhancing algorithms providing factorization and multiply-add extraction heuristics and choice criteria based on a simple cost model. This paper describes our approach and a first implementation. Experiments on real code, including an excerpt from SPEC FP95, are very promising since we automatically obtain the same results as manual transformations, with a performance improvement by a factor of up to three.

关键词： Costs Computer applications Application software Hardware parallel processing Mathematics Runtime Computational efficiency Mathematical programming Pipeline processing

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Predicate control for active debugging of distributed programs

Predicate control for active debugging of distributed progra...

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international symposium on parallel Processing

作者： A. Tarafdar V.K. Garg Department of Computer Sciences University of Texas Austin Austin TX USA Department of Electrical and Computer Engineering University of Texas Austin Austin TX USA

Existing approaches to debugging distributed systems involve a cycle of passive observation followed by computation replaying. We propose predicate control as an active approach to debugging such systems. The predicate control approach involves a cycle of observation followed by controlled replaying of computation, based on observation. We formalize the predicate control problem for both off-line and on-line scenarios. We prove that off-line predicate control for general boolean predicates is NP-hard. However, we provide an efficient solution for off-line predicate control for the class of disjunctive predicates. We further solve on-line predicate control for disjunctive predicates under certain restrictions on the system. Lastly, we demonstrate how both off-line and on-line predicate control facilitate distributed debugging by allowing the programmer to control computations to maintain global safety properties.

关键词： Debugging Computer bugs Distributed computing Control systems Safety Distributed control programming profession Acceleration USA Councils Detection algorithms

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On evolving hardware: on-line evolution by cellular programming

On evolving hardware: on-line evolution by cellular programm...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： G.M. Nicoletti University of Pittsburgh Greensburg USA

Extensive research shows that the implementation of evolutionary algorithms are costly in many cases. This paper reports on an alternative construction, namely non-uniform cellular automatons (CA) with which (1) it is possible to increase the capacity for complex computations while preserving the main features of CAs, (2) evolve parallel cellular machines to perform computational tasks via cellular programming, and (3) attain evolware with implementations centering on hardware. The hardware architecture of the cellular programming evolware involves: (1) a group of individual cells is in operation rather than a single one, (2) genetic operators are implemented on-board rather than on offline computer, and (3) the evolutionary phase proceeds uninterrupted via a continuous machine's operation. The active components of the evolware complex comprise exclusively the latest cellular FPGA circuit. Accordingly, this paper is organized as follows: Section I presents fundamentals and analysis of computations in quasiuniform cellular automats in a quasi-uniform cellular space; Section II introduces the basic approach for coevolving cellular computation and cellular machines, denoted cellular programming. Section III adopts synchronization as a criteria to attain evolware centered on hardware. Cellular programming is implemented in hardware. The algorithm is slightly modified (without loss of performance): the genetic operators, one-point crossover and mutation, are replaced with the operator uniform crossover. This results in the creation of an offspring genome from two parent genomes (bit strings) with a 50% probability for each parent. Finally, Section IV analyzes performance and results.

关键词： Hardware Genetic programming Concurrent computing Automatic programming Genomics Bioinformatics Evolutionary computation Automata Content addressable storage parallel programming

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A software architecture for global address space communication on clusters: put/get on fast messages 98

A software architecture for global address space communicati...

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international symposium on High Performance Distributed Computing

作者： L.A. Giannini A.A. Chien Department of Computer Science University of Illinois Urbana-Champaign USA University of California San Diego La Jolla CA USA

ISBN: (纸本)9780818685798

Global address space parallel programming models can be an effective alternative to send/receive style communication, simplifying programming or code generation and increasing performance for certain application types. Traditionally, global address space mechanisms have been implemented in hardware in order to provide the necessary communication performance and responsiveness. However new high performance cluster messaging systems now allow global address space mechanisms to be realized efficiently in software. We describe a high performance one sided communication model that is implemented as a software layer on top of the Illinois Fast Messages (FM) system. We evaluate several different software implementation architectures for the remote agent, characterizing their differing performance characteristics. Our Put/Get FM implementation achieves peak bandwidths for put/get operations of 67 MBytes/s, overheads of a few microseconds, and remote read latencies as low as 26 microseconds on a Myrinet connected PC cluster. This implementation was released publicly as part of HPVM 1.0 in August 1997, and is receiving significant usage. It has been used for an implementation of the Global Arrays library and also serves as a back-end target for PGI's commercial HPF compiler.

关键词： Software architecture Software performance parallel programming Delay Application software Hardware Communication system software Computer architecture Bandwidth Libraries

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Graph transformation for communication minimization using retiming

Graph transformation for communication minimization using re...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： M. Sheliga Zhihong Yu Fei Chen E.H.-M. Sha Department of Computer Science & Engineering University of Notre Dame Notre Dame IN USA

Nested loops are normally the most time intensive tasks in computer algorithms. These loops often include multiple dependencies between arrays that impose communication constraints when used in multiprocessor systems. These dependencies may be between dependent arrays (loop dependencies), or between independent arrays (data dependencies). In this paper, reducing the communication caused by data and loop dependencies for perfect nested loops is explored. It is shown that for a given partition data dependencies may be treated as a specialized form of loop dependencies. Once this is done, previous results on scalable loop tiling can be used to calculate the final total communication. Next, the effects of changing the partition for both loop and data communication are examined. Using these results, the optimal partition for a number of cases is examined. Results are shown which illustrate the efficiency of the system as well as the savings achieved.

关键词： parallel architectures Signal processing algorithms Digital signal processing Delay Computer science Multiprocessing systems Data communication Image processing Programmable control Adaptive control

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Breaking the Barriers: Two Models for MPI programming 98

Breaking the Barriers: Two Models for MPI Programming

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Proceedings of the 1998 international Conference on parallel architectures and Compilation Techniques

作者： Jose Luis Roda Casiano Rodriguez-Leon Daniel Gonzalez-Morales Francisco Almeida-Rodriguez Pablo Pulido Daniel Dorta

ISBN: (纸本)9780818685910

The asynchronous nature of many MPI/PVM programs does not fit the BSP model. The barrier synchronization imposed by the model restricts the range of available algorithms and their performance. Through the suppression of barriers and the generalization of the concept of superstep we propose two new models, the BSP-like and the BSP Without Barriers (BSPWB) models. While the BSP-like extends the BSP* model to programs written using collective operations, the more general BSPWB model admits the MPI/PVM parallel asynchronous programming style. As LogP, the model encourages locality but it is simpler to use. The parameters of the models and their quality are evaluated on a distributed-shared memory machine, the Origin 2000 and on a distributed memory machine, the CRAY T3E. The dependence of the time spent in an h-relation is stronger in the communication pattern than in the number of processors. The total variation of the h-relation time in both the patterns and processor numbers is smaller than sixty nanoseconds. To illustrate the proposed models, two different applications are considered: a parallel Sort using Regular Sampling (PSRS) and a parallel Dynamic programming Algorithm solving the Single Resource Allocation Problem (SRAP). The PSRS is a synchronous algorithm with a rich set of collective communication patterns and coarse grain communications. On the opposite extreme, the SRAP is a fine grain communication algorithm using permutation patterns. The computational results prove the accuracy of the models. The prediction of the communication times is robust even for the SRAP, where communication is dominated by small messages.

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Predicting indirect branches via data compression

Predicting indirect branches via data compression

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IEEE/ACM international symposium on Microarchitecture (MICRO)

作者： J. Kalamatianos D.R. Kaeli Department of Electrical and Computer Engineering Northeastern University Boston MA USA

Branch prediction is a key mechanism used to achieve high performance on multiple issue, deeply pipelined processors. By predicting the branch outcome at the instruction fetch stage of the pipeline, superscalar processors become able to exploit Instruction Level parallelism (ILP) by providing a larger window of instructions. However, when a branch is mispredicted, instructions from the mispredicted path must be discarded. Therefore, branch prediction accuracy is critical to achieve high performance. Existing branch prediction schemes can accurately predict the direction of conditional branches, but have difficulties predicting the correct targets of indirect branches. Indirect branches occur frequently in Object-Oriented Languages (OOL), as well as in Dynamically-Linked Libraries (DLLs), two programming environments rapidly increasing in popularity. In addition, certain language constructs such as multi-way control transfers (e.g., switches), and architectural features such as 64-bit address spaces, utilize indirect branching. In this paper, we describe a new algorithm for predicting unconditional indirect branches called Prediction by Partial Matching (PPM). We base our approach on techniques proven to work optimally in the field of data compression. We combine a viable implementation of the PPM algorithm with dynamic per-branch selection of path-based correlation and compare its prediction accuracy against a variety of predictors. Our results show that, for approximately the same hardware budget, the combined predictor can achieve a misprediction ratio of 9.47%, as compared to 11.48% for the previously published most accurate indirect branch predictor.

关键词： Data compression Accuracy Pipelines parallel processing Libraries programming environments Switches Electronic switching systems Prediction algorithms Heuristic algorithms

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3rd international symposium on parallel architectures, algorithms, and Networks, I-SPAN 1997

3rd International Symposium on Parallel Architectures, Algor...

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3rd international symposium on parallel architectures, algorithms, and Networks, I-SPAN 1997

The proceedings contain 78 papers. The topics discussed include: a new general purpose parallel database system;a parallel pipelined renderer for time-varying volume data;wavelength division multiple access ring-virtual topology on a simple ring network;features of optical interconnects in distributed-shared memory organized MIMD architectures: the ultimate goal;optimal realization of hypercubes by three-dimensional space-invariant optical interconnections;critical sections and producer/consumer queues in weak memory systems;a scalable cache coherent architecture for large-scale mesh-connected multiprocessors;exploiting global data locality in non-blocking multithreaded architectures;an implementable dynamic automatic self-stabilizing protocol;cover model: a framework for design and execution of distributed applications;a new shortest path routing algorithm and embedding cycles of crossed cube;algorithms and lower bounds for p-gossiping in circulant networks;and fiber-ribbon pipeline ring network for high-performance distributed computing systems.

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Proceedings of the 1997 international symposium on parallel architectures, algorithms and Networks (I-SPAN'97)

Proceedings of the 1997 International Symposium on Parallel ...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

Presents the title page of the proceedings record.

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