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24th international Conference on algorithms and architectures for parallel Processing, ICA3PP 2024

24th International Conference on Algorithms and Architecture...

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24th international Conference on algorithms and architectures for parallel Processing, ICA3PP 2024

ISBN: (纸本)9789819615476

The proceedings contain 131 papers. The special focus in this conference is on algorithms and architectures for parallel Processing. The topics include: MARO: Enabling Full MPI Automatic Refactoring in DSL-Based programming Framework;SSC: An SRAM-Based Silence Computing Design for On-chip Memory;TP-BFT: A Faster Asynchronous BFT Consensus with parallel Structure;LTP: A Lightweight On-Chip Temporary Prefetcher for Data-Dependent Memory Accesses;A Neural Network-Based PUF Protection Method Against Machine Learning Attack;Compression Format and Systolic Array Structure Co-design for Accelerating Sparse Matrix Multiplication in DNNs;multidimensional Intrinsic Identity Construction and Dynamic Seamless Authentication Schemes in IoT Environments;invisible Backdoor Attack with Image Contours Triggers;finestra: Multi-aggregator Swarm Learning for Gradient Leakage Defense;DIsFU: Protecting Innocent Clients in Federated Unlearning;multiple-Round Aggregation of Abstract Semantics for Secure Heterogeneous Federated Learning;dynamic Privacy Protection with Large Language Model in Social Networks;a Dynamic Symmetric Searchable Encryption Scheme for Rapid Conjunctive Queries;a Data Watermark Scheme Base on Data Converted Bitmap for Data Trading;distributed Incentive Algorithm for Fine-Grained Offloading in Vehicular Ad Hoc Networks;mitigating Over-Unlearning in Machine Unlearning with Synthetic Data Augmentation;AW-YOLOv9: Adverse Weather Conditions Adaptation for UAV Detection;efficient and Privacy-Preserving Ranking-Based Federated Learning;on-Chain Dynamic Policy Evaluation for Decentralized Access Control;DPG-FairFL: A Dual-Phase GAN-Based Defense Framework Against Image-Based Fairness Data Poisoning Attacks in Federated Learning.

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24th international Conference on algorithms and architectures for parallel Processing, ICA3PP 2024

24th International Conference on Algorithms and Architecture...

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24th international Conference on algorithms and architectures for parallel Processing, ICA3PP 2024

ISBN: (纸本)9789819615506

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24th international Conference on algorithms and architectures for parallel Processing, ICA3PP 2024

24th International Conference on Algorithms and Architecture...

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24th international Conference on algorithms and architectures for parallel Processing, ICA3PP 2024

ISBN: (纸本)9789819615445

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SPARK: Sparsity Aware, Low Area, Energy-Efficient, Near-memory Architecture for Accelerating Linear programming Problems 31

SPARK: Sparsity Aware, Low Area, Energy-Efficient, Near-memo...

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31st IEEE international symposium on High Performance Computer Architecture, HPCA 2025

作者： Raman, Siddhartha Raman Sundara John, Lizy Kulkarni, Jaydeep P. The University of Texas at Austin United States

ISBN: (纸本)9798331506476

Integer Linear programming (ILP) is an important mathematical approach for solving time-sensitive real-life optimization problems, including network routing, map routing, traffic scheduling, etc. However, the algorithms for solving ILPs are typically sparse and branch-intensive, and not CPU/GPU friendly. In the paper 'What could a million cores do to solve Integer programs', Koch et al. [40] presented data illustrating that Integer Linear programming (ILP) applications take tens of hours of execution time even on the largest parallel computers. Long execution time is a problem because many real-life applications need a decision in seconds or minutes. The widely used ILP solvers, like Gurobi (optimized for CPUs), perform software-based optimizations to handle the inherent sparsity in ILPs but still do not meet decision threshold because of the limited throughput of CPUs. GPUs are suited for large-sized dot-product compute, however, GPU-based ILP solvers also do not meet decision thresholds as (i) GPU is not sparsity friendly and (ii) GPU incurs thread divergence for branching, resulting in under-utilization of streaming engines and periodic host-GPU interaction. We propose SPARK, a sparsity-aware, reuse-aware, energy-efficient, reconfigurable, near-cache ILP architecture that (i) re-configures the existing L1 cache present in CPUs to perform near-cache acceleration with easy integration into the baseline CPU pipeline with minimal area overhead (∼ 1.4% of a CPU), (ii) performs near-cache sparsity detection and sparsity-aware compute, reducing the number of insignificant computations, and data movement energy overheads, (iii) leverages the computational patterns present in algorithms used for solving ILP to realize a reuse-aware architecture, and (iv) is applicable to solving sparse and dense ILPs and LPs (Linear Programs). We observe 15 x / 20 x, and 152 x / 740 x performance/energy improvement over AMD's Zen3 CPU, and Nvidia's Tesla v100 GPU for sparse reallife ILPs

关键词： Reconfigurable architectures

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MARO: Enabling Full MPI Automatic Refactoring in DSL-Based programming Framework 24th

MARO: Enabling Full MPI Automatic Refactoring in DSL-Based ...

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24th international Conference on algorithms and architectures for parallel Processing, ICA3PP 2024

作者： Lei, Tong Chen, Zongjing Che, Yonggang Xu, Chuanfu Laboratory of Digitizing Software for Frontier Equipment National University of Defense Technology Changsha410073 China National Key Laboratory of Parallel and Distributed Computing College of Computer Science and Technology National University of Defense Technology Changsha410073 China

ISBN: (纸本)9789819615445

Currently, the landscape of computer hardware architecture presents the characteristics of heterogeneity and diversity, prompting widespread attention to cross-platform portable parallel programming techniques. Most existing portable programming approaches adopt the "MPI+X" strategy, focusing mainly on node-level "X" parallelism, while inter-node parallelization still relies on manual MPI programming. OP2 is a domain-specific language-based portable parallel programming framework for unstructured mesh applications that supports the automatic generation of MPI parallel code. However, programmers must manually write pre-processing code during code refactoring, such as handling the mapping relationship between global and process-local variables and the initial distribution of process-local data. In this paper, we propose MARO (MPI Automatic Refactoring for OP2), an automatic refactoring method for generating pre-processing code targeting MPI code generation within the OP2 programming framework for unstructured mesh applications. This method automatically generates the pre-processing code required for MPI parallelism through the source-to-source translator, enabling OP2 to generate MPI parallel code without requiring users to write MPI-related code manually. We compare the automatically refactored OP2 applications using the proposed method with those manually refactored to validate its effectiveness. The proposed method enhances OP2’s automatic parallel code generation capability, enabling it to achieve fully automatic MPI parallelization. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Automatic programming

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Vectron: A Dynamic programming Auto-vectorization Framework 25

Vectron: A Dynamic Programming Auto-vectorization Framework

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23rd ACM/IEEE international symposium on Code Generation and Optimization, CGO 2025

作者： Moghaddasi, Sourena Naser Smajlović, Haris Shajii, Ariya Numanagić, Ibrahim University of Victoria Victoria Canada Exaloop Boston United States

ISBN: (纸本)9798400712753

Dynamic programming (DP) is a fundamental algorithmic strategy that decomposes large problems into manageable subproblems. It is a cornerstone of many important computational methods in diverse fields, especially in the field of computational genomics, where it is used for sequence comparison. However, as the scale of the data keeps increasing, these algorithms are becoming a major computational bottleneck, and there is a need for strategies that can improve their performance. Here, we present Vectron, a novel auto-vectorization suite that targets array-based DP implementations written in Python and converts them to efficient vectorized counterparts that can efficiently process multiple problem instances in parallel. Leveraging Single Instruction Multiple Data (SIMD) capabilities in modern CPUs, along with Graphics Processing Units (GPUs), Vectron delivers significant speedups, ranging from 10% to more than 20×, over the conventional C++ implementations and manually vectorized and domain-specific state-of-the-art implementations, without necessitating large algorithm or code changes. Vectron’s generality enables automatic vectorization of any array-based DP algorithm and, as a result, presents an attractive solution to optimization challenges inherent to DP algorithms. © 2025 Copyright held by the owner/author(s).

关键词： Graphics processing unit

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Fat-Tree QRAM: A High-Bandwidth Shared Quantum Random Access Memory for parallel Queries 25

Fat-Tree QRAM: A High-Bandwidth Shared Quantum Random Access...

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30th ACM international Conference on Architectural Support for programming Languages and Operating Systems, ASPLOS 2025

作者： Xu, Shifan Lu, Alvin Ding, Yongshan Yale Quantum Institute Yale University New HavenCT United States

ISBN: (纸本)9798400710797

Quantum Random Access Memory (QRAM) is a crucial architectural component for querying classical or quantum data in superposition, enabling algorithms with wide-ranging applications in quantum arithmetic, quantum chemistry, machine learning, and quantum cryptography. In this work, we introduce Fat-Tree QRAM, a novel query architecture capable of pipelining multiple quantum queries simultaneously while maintaining desirable scalings in query speed and fidelity. Specifically, Fat-Tree QRAM performs O(log(N)) independent queries in O(log(N)) time using O(N) qubits, offering immense parallelism benefits over traditional QRAM architectures. To demonstrate its experimental feasibility, we propose modular and on-chip implementations of Fat-Tree QRAM based on superconducting circuits and analyze their performance and fidelity under realistic parameters. Furthermore, a query scheduling protocol is presented to maximize hardware utilization and access the underlying data at an optimal rate. These results suggest that Fat-Tree QRAM is an attractive architecture in a shared memory system for practical quantum computing. © 2025 ACM.

关键词： Quantum cryptography

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NPB-PSTL: C++ STL algorithms with parallel Execution Policies in NAS parallel Benchmarks

NPB-PSTL: C++ STL Algorithms with Parallel Execution Policie...

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Euromicro Conference on parallel, Distributed and Network-Based Processing

作者： Júnior Löff Renato B. Hoffmann Arthur S. Bianchessi Leonardo Mallmann Dalvan Griebler Walter Binder Faculty of Informatics Università della Svizzera italiana (USI) Lugano Switzerland Pontifical Catholic University of Rio Grande do Sul (PUCRS) Porto Alegre Brazil

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

The C++ language continually evolves through formal specifications established by its standards committee, proposing new features to maintain $\mathrm{C}++$ as a relevant programming language while improving usability, performance, and portability across platforms. With the addition of parallel Standard Template Library (STL) algorithms in C++17, programmers can now leverage parallel processing capabilities via vendor-neutral parallel execution policies. This study presents an adaptation of the NAS parallel Benchmarks (NPB)—a well-established suite of applications for evaluating parallel architectures-by porting its sequential C-style code to use C++ STL abstractions and performance-portable parallelism features. Our goals are to (1) assess the suitability of C++ STL for scientific applications like the ones in the NPB and (2) provide a comparative performance and portability of STL algorithms’ parallel execution policies across different multicore architectures (x86 and AArch64). Results indicate that the performance of parallel STL algorithms is often close to that of optimized handwritten versions (OpenMP, Intel TBB, and FastFlow) on different architectures, with notable shortfalls. Across all NPB benchmarks, the STL algorithms’ geometric mean shows sequential execution times that are between 3.76% and $\mathrm{6. 9 \%}$ higher, while parallel executions may reach a geometric mean of up to $\mathrm{2 1. 2 1 \%}$ higher execution time.

关键词： parallel programming Multicore processing Software algorithms C++ languages Benchmark testing parallel processing Data structures Libraries Hardware Standards

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Enhancing Delay-Sensitive Task Offloading: A Multi-agent Deep Reinforcement Learning Algorithm for MEC-Based AIoT Systems 24th

Enhancing Delay-Sensitive Task Offloading: A Multi-agent Dee...

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24th international Conference on algorithms and architectures for parallel Processing, ICA3PP 2024

作者： Tang, Fengjie Xu, Jia Liu, Xiao Yao, Aiting Fang, Mingyan Li, Xuejun Anhui Provincial International Joint Research Center for Advanced Technology in Medical Imaging School of Computer Science and Technology Anhui University Hefei China School of Information Technology Deakin University Geelong Australia

ISBN: (纸本)9789819615414

Artificial Intelligence of Things (AIoT) systems are widely utilized in various domains such as smart logistics and smart health. In AIoT systems, computational tasks earmarked for offloading by IoT devices often have different task priorities and heterogeneous resource requirements. However, these factors will affect the QoS of the solution and the task response time. Therefore, motivated by a typical smart warehouse system, a Multi-access Edge Computing (MEC) based distributed task offloading framework is proposed. Afterward, a delay-sensitive mixed-integer programming model is defined to address the imbalanced utilization of computing resources between edge and cloud servers during the offloading process. Finally, based on the attention mechanism, a Priority-Driven Multi-Agent Deep Reinforcement Learning algorithm (PDMA-DRL) is proposed to fulfill real-time resource requirements while reducing the task response time. The PDMA-DRL algorithm consists of two agents, and each agent corresponds to a sub-problem. Comprehensive experimental results demonstrate that our proposed PDMA-DRL algorithm can outperform representative existing methods in generating delay-sensitive task offloading plans and effectively reducing the task response time. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Deep reinforcement learning

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Reuse-Aware Compilation for Zoned Quantum architectures Based on Neutral Atoms

Reuse-Aware Compilation for Zoned Quantum Architectures Base...

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IEEE symposium on High-Performance Computer Architecture

作者： Wan-Hsuan Lin Daniel Bochen Tan Jason Cong University of California Los Angeles Department of Physics Harvard University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Quantum computing architectures based on neutral atoms offer large scales and high-fidelity operations. They can be heterogeneous, with different zones for storage, entangling operations, and readout. Zoned architectures improve computation fidelity by shielding idling qubits in storage from side-effect noise, unlike monolithic architectures where all operations occur in a single zone. However, supporting these flexible architectures with efficient compilation remains challenging. In this paper, we propose ZAC, a scalable compiler for zoned architectures. ZAC minimizes data movement overhead between zones with qubit reuse, i.e., keeping them in the entanglement zone if an immediate entangling operation is pending. Other innovations include novel data placement and instruction scheduling strategies in ZAC, a flexible specification of zoned architectures, and an intermediate representation for zoned architectures, ZAIR. Our evaluation shows that zoned architectures equipped with ZAC achieve a 22x improvement in fidelity compared to monolithic architectures. Moreover, ZAC is shown to have a 10% fidelity gap on average compared to the ideal solution. This significant performance enhancement enables more efficient and reliable quantum circuit execution, enabling advancements in quantum algorithms and applications. ZAC is open source at https://***/UCLAVAST/ZAC

关键词： Technological innovation Quantum algorithm Program processors Scheduling algorithms Qubit Computer architecture Atoms parallel processing Integrated circuit reliability Quantum circuit

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