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检索条件"任意字段=International Symposium on Parallel Architectures, Algorithms, and Programming"

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On deciding granularity for optimal speedup for solving data parallel problems with clustered distributed computing

On deciding granularity for optimal speedup for solving data...

引用

international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Jung-Sing Jwo Yu Chin Cheng Chin-Yun Hsieh Department of Computer and Information Sci Tunghai University Taichung Taiwan Department of Electronic Engr. National Taipei University of Technology Taipei Taiwan

ISBN: (纸本)0818682596

In this paper we show how to obtain optimal speedup in a master-slave model for solving data-parallel problems. Given the number of homogeneous workstations, their computation time for solving a basic sub-task of the problem, network transmission bandwidth and data volume per basic sub-task, the per-distribution number of basic sub-tasks sent to a slave for attaining the optimal speedup can be decided. The effectiveness of the proposed theory has been tested using a parallel computing experiment involving the Hough transformation.

关键词： Workstations Distributed computing Local area networks Bandwidth Concurrent computing Master-slave Computer networks Grain size High performance computing parallel processing

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The Sisal model of functional programming and its implementation

The Sisal model of functional programming and its implementa...

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Aizu international symposium on parallel algorithms/Architecture Synthesis

作者： J.-L. Gaudiot W. Bohm W. Najjar T. DeBoni J. Feo P. Miller Department of Electrical Engineering-Systems University of Southern California Los Angeles CA USA Computer Science Department Colorado State University Fort Collins CO USA Computer Research Group Lawrence Livemore National Laboratory Livermore CA USA CaeSoft Development Tracy CA USA

programming a massively-parallel machine is a daunting task for any human programmer, and parallelization may even be impossible for any compiler. Instead, the functional programming paradigm may prove to be an ideal solution by providing an implicitly parallel interface to the programmer. We describe the Sisal (Stream and Iteration in a Single Assignment Language) project. Its goal is to provide a general-purpose user interface for a wide range of parallel processing platforms.

关键词： Functional programming parallel programming Concurrent computing programming profession Laboratories Program processors parallel processing Costs Computer science Humans

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Signal processing at 250 MHz using high-performance FPGA's 97

Signal processing at 250 MHz using high-performance FPGA's

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Proceedings of the 1997 ACM 5th international symposium on Field-Programmable Gate Arrays, FPGA

作者： Von Herzen, Brian Rapid Prototypes Inc Carson City NV United States

ISBN: (纸本)9780897918015

This paper describes an application in high-performance signal processing using reconfigurable computing engines. The application is a 250 MHz cross-correlator for radio astronomy and was developed using the fastest available Xilinx FPGA's. We will report experimental results on the operation of CMOS FPGA's at 250 MHz, and describe the architectural innovations required to build a 250 MHz reconfigurable signal processor. Extensions of the technique to a variety of high-performance real-time signal processing algorithms are discussed. The results of this design work provide important clues as to how to improve FPGA architectures to better support real-time signal processing at hundreds of MHz. In particular, direct routing resources between logic elements are critical to preserving high performance. These routing resources need to be symmetric in order to allow for two-way communications between logic elements. Four-way symmetry and regularity would allow for orthogonal transformations of processing elements in a hierarchical fashion. Finally, experimental results indicate that clock buffering is frequently the cause of ultimate failure in speed and performance tests. Wave pipelining techniques may be suitable in clock distribution to improve performance to match that of other elements in the system.

关键词： parallel processing systems

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HiPAR-DSP: a parallel VLIW RISC processor for real time image processing applications

HiPAR-DSP: a parallel VLIW RISC processor for real time imag...

引用

IEEE international Conference on algorithms and architectures for parallel Processing (ICAP)

作者： J.P. Wittenburg M. Ohmacht J. Kneip W. Hinrichs P. Pirsch Laboratorium für Informationstechnologie Universität Hannover Hanover Germany

Derived from a thorough analysis of a wide class of image processing algorithms' properties, a parallel RISC architecture has been developed. The architecture gains performance from data level parallelism as well as from instruction level parallelism. From the beginning of the concept phase, high-level programming capabilities have been one of the major design goals. Thus, there has been a steady interaction between the design of the software development toolkit-optimizing assembler and C++ compiler-and the architecture itself. The RISC-typical register files are one of the most critical elements as well concerning die size and clock frequency as the assembler's ability in VLIW scheduling. Running at 100 MHz (200 mm/sup 2/, 0.35 /spl mu/m CMOS) the processor reaches a sustained performance of more than 2 GOPS for a wide range of image processing algorithms.

关键词： VLIW Reduced instruction set computing Computer architecture Image processing Assembly Image analysis Algorithm design and analysis Performance gain Software design programming

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Cyclic networks: A family of versatile fixed-degree interconnection architectures

Cyclic networks: A family of versatile fixed-degree intercon...

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international symposium on parallel Processing

作者： C.-H. Yeh B. Parhami Department of Electrical and Computer Engineering University of California Santa Barbara CA USA

In this paper, we propose a new family of interconnection networks, called cyclic networks (CNs), in which an intercluster connection is defined on a set of nodes whose addresses are cyclic shifts of one another. The node degrees of basic CNs are independent of system size, but can vary from a small constant (e.g., 3) to as large as required, thus providing flexibility and effective tradeoff between cost and performance. The diameters of suitably constructed CNs can be asymptotically optimal within their lower bounds, given the degrees. We show that packet routing and ascend/descend algorithms can be performed in /spl Theta/(log/sub d/ N) communication steps on some CNs with N nodes of degree /spl Theta/(d). Moreover CNs can also efficiently emulate homogeneous product networks (e.g., hypercubes and high dimensional meshes). As a consequence, we obtain a variety of efficient algorithms on such networks, thus proving the versatility of CNs.

关键词： Costs Hypercubes Multiprocessor interconnection networks Computer architecture Routing Network topology Algorithm design and analysis parallel programming Scalability Hardware

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Design issues in building Web-based parallel programming environments 97

Design issues in building Web-based parallel programming env...

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international symposium on High Performance Distributed Computing

作者： K. Dincer G.C. Fox Northeast Parallel Architectures Center and Department of Electrical Engineering and Computer Science Syracuse University Syracuse NY USA

ISBN: (纸本)9780818681172

We exploited the recent advances in Internet connectivity and Web technologies for building Web-based parallel programming environments (WPPEs) that facilitate the development and execution of parallel programs on remote high-performance computers. A Web browser running on the user's machine provides a user-friendly interface to server-site user accounts and allows the use of parallel computing platforms and software in a convenient manner. The user may create, edit, and execute files through this Web browser interface. This new Web-based client-server architecture has the potential of being used as a future front-end to high-performance computer systems. We discuss the design and implementation of several prototype WPPEs that are currently in use at the Northeast parallel architectures Center and the Cornell Theory Center. These initial prototypes support high-level parallel programming with Fortran 90 and High Performance Fortran (HPF), as well as explicit low-level programming with Message Passing Interface (MPI). We detail the lessons learned during the development process and outline the tradeoffs of various design choices in the realization of the design. We especially concentrate on providing server-site user accounts, mechanisms to access those accounts through the Web, and the Web-related system security issues.

关键词： Buildings parallel programming Prototypes Internet Concurrent computing parallel processing Computer architecture Software prototyping parallel architectures Message passing

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Portable multiprecision arithmetic package based on message passing interface

Portable multiprecision arithmetic package based on message ...

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Aizu international symposium on parallel algorithms/Architecture Synthesis

作者： A.P. Vazhenin V.A. Morozov Supercomputer Software Department RAS Russia Faculty of Mathematics and Informatic Novosibirsk State Technical University Russia

Multiprecision arithmetic allows one to significantly reduce the influence of rounding errors in cases when the standard data representation does not support the required accuracy. In this paper, we discuss an effective programming technology for supporting a given accuracy of calculations in a suitable time by a complex method using multiprecision arithmetic, dynamically changeable operand length and parallel data processing. The distinguishing feature of the proposed approach is that the initial highly parallel algorithm can be adapted to computations with variable data capacity. A library is described for supporting this technology on parallel computers with a message passing interface for the communications. Some examples of the solution of typical problems are presented.

关键词： Arithmetic Packaging Message passing Concurrent computing Roundoff errors Dynamic programming parallel programming Accuracy Data processing parallel algorithms

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A simulation study of dynamic load balancing for network-based parallel processing

A simulation study of dynamic load balancing for network-bas...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Wentong Cai Bu-Sung Lee A. Heng Li Zhu School of Applied Science Nanyang Technological University Singapore Singapore Department of Computer Science & Engineering Pénnsylvania State University PA USA

A simulation study of dynamic load balancing for parallel processing on network of workstations (NOW) is presented in this paper. A simulation model is constructed. It includes a representative CPU scheduling policy, and also considers the message exchange, task transfer and migration costs explicitly. A global dynamic load balancing algorithm is simulated. Both task transfer and task migration are considered. The performance of the algorithm under both homogeneous and heterogeneous environments is analyzed. In addition, the interaction of parallel and sequential workloads on an NOW is also examined. Our results show that dynamic load balancing can achieve better performance improvement for heterogeneous systems than for homogeneous systems; it is especially effective in a system where both parallel and sequential tasks concurrently exist; and the use of task migration generally does not further improve performance.

关键词： Load management parallel processing Costs Workstations Heuristic algorithms Performance analysis Algorithm design and analysis Hardware Computer networks Concurrent computing

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The Pilgrim: a new consistency protocol for distributed shared memory

The Pilgrim: a new consistency protocol for distributed shar...

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IEEE international Conference on algorithms and architectures for parallel Processing (ICAP)

作者： H. Guyennet J.-C. Lapayre M. Trehel Laboratoire d''informatique-UFR Sciences et Techniques Besancon France

We propose a new consistency protocol named Pilgrim for distributed shared memory (DSM) where different shared objects are replicated at each site. This protocol provides both reliable consistency and guaranteed perfo... 详细信息

关键词： Protocols Automata Writing Memory management Token networks programming profession Maintenance Delay Collaborative work Data structures

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RMESH algorithms for parallel string matching

RMESH algorithms for parallel string matching

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Hsi-Chieh Lee F. Ercal Information Management Department Yuan-Ze University Chungli Taiwan Computer Science Department University of Missouri Rolla Rolla MO USA

String matching problem received much attention over the years due to its importance in various applications such as text/file comparison, DNA sequencing, search engines, and spelling correction. Especially with the introduction of search engines dealing with tremendous amount of textual information presented on the world wide web and the research on DNA sequencing, this problem deserves special attention and any algorithmic or hardware improvements to speed up the process will benefit these important applications. In this paper, we present three algorithms for string matching on reconfigurable mesh architectures. Given a text T of length n and a pattern P of length m, the first algorithm finds the exact matching between T and P in O(1) time on a 2-dimensional RMESH of size (n-m+1)/spl times/m. The second algorithm finds the approximate matching between T and P in O(k) time on a 2D RMESH, where k is the maximum edit distance between T and P. The third algorithm allows only the replacement operation in the calculation of the edit distance and finds an approximate matching between T and P in constant-time on a 3D RMESH.

关键词： Pattern matching DNA Search engines parallel algorithms Algorithm design and analysis Web sites Hardware Text processing Pattern recognition Costs

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