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检索条件"任意字段=International Symposium on Parallel Architectures, Algorithms, and Programming"

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A distributed environment for hypercube computing

A distributed environment for hypercube computing

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Aizu international symposium on parallel algorithms/Architecture Synthesis

作者： Jung-Sing Jwo Shi-Sen Chang Yi-Cheng Chen D.F. Hsu Department of Computer and Information Sciences Tunghai University Taichung Taiwan Graduate Program in Computer Science Fordham University New York NY USA

Proposes a distributed computing environment, called the Virtual Cube (VC), to support arbitrarily large binary hypercube computing on a cluster of homogeneous workstations that are interconnected by an Ethernet LAN. The embedding concept between binary hypercube parallel architectures is introduced, and the concept of a cluster of computers interconnected through a computer network. In VC, a SIMD parallel language called VCPL (VC parallel Language) is provided. The advantages of the VC system are that (a) it can be considered as a practical and economical binary hypercube machine, and (b) it brings parallel solutions on a binary hypercube directly into distributed applications. Currently, a VC prototype is implemented on NeXT workstations.

关键词： Hypercubes Distributed computing Virtual colonoscopy Workstations LAN interconnection Computer networks parallel languages Ethernet networks Local area networks parallel architectures

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Lazy decomposition: a novel technique to control parallel task granularity

Lazy decomposition: a novel technique to control parallel ta...

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IEEE international Conference on algorithms and architectures for parallel Processing (ICAP)

作者： Suntae Hwang Hojung Cha Department of Computer Science Kookmin University South Korea Department of Computer Science Kwangwoon University South Korea

ISBN: (纸本)0780342291

This paper introduces a new mechanism for the exposure of large grain parallelism. The scheme performs lazy task creation; inlining all tasks provisionally and extracting parallelism from the inlined information later on demand. However, unlike other mechanisms, the further task demand is satisfied by the next evaluation stream rather than retrospectively reversing the inlining decision of the current stream. The scheme is called lazy decomposition because decomposition itself is throttled rather than just the extraction of a task. Lazy decomposition makes the serial section clearly separated from the parallel section in an evaluation tree for a particular function, and this allows the serial section to adopt a sequential algorithm. The performance improvement is significant in divide-and-conquer applications by adoption of sequential algorithms.

关键词： parallel machines Yarn Computer science Data mining programming profession Program processors parallel processing Load management Cost function Heuristic algorithms

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A decentralised scheme for multi-node broadcasting on hypercubes

A decentralised scheme for multi-node broadcasting on hyperc...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Y. Hayakawa S. Fujita M. Yamashita Department of Electrical Engineering Faculty of Engineering Hiroshima University Higashihiroshima Japan

In this paper, we study the following multi-node broadcast problem on hypercubes, which is an asynchronous and repetitive version of all-to-all broadcast problem. Suppose that nodes of a hypercube asynchronously repeat broadcasting a piece of information called a token. They can asynchronously initiate their broadcasts while other broadcasts are in process. The multi-node broadcast problem, which we discuss in this paper, is the problem of completing each of these broadcasts quickly. It is neither the broadcast problem, which assumes that no nodes initiate a broadcast while a broadcast is in process, nor the gossip problem, which assumes that all nodes initiate broadcasts simultaneously. We propose an adaptive scheme SORT for solving the problem in such a way that each initiator of a broadcast determines the broadcast route based only on local information. The effectiveness of SORT is demonstrated by simulations.

关键词： Broadcasting Hypercubes Algorithm design and analysis Computer networks Concurrent computing Network topology Computational modeling Computer simulation parallel processing Load management

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The architecture of OCMP and its evaluation

The architecture of OCMP and its evaluation

引用

international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： K. Saisho T. Sano A. Fukuda Graduate Sch. of Inf. Sci. Nara Inst. of Sci. & Technol. Takayama Japan

By gathering multiple processors in one LSI chip, communication delay between processors becomes shorter and then efficient fine/medium grain parallel processing can be realized. The authors propose a new processor architecture called OCMP (On-Chip Multi-Processing Architecture). OCMP has two characteristics: one is the instruction level dispatching mechanism; and the other is the divided cache system. OCMP employs a fork-join type parallel processing model in order to simplify the dispatching mechanism. By dividing the cache system into shared cache and private cache, the cache coherence problem between processors on the same chip is removed and access conflict on the shared cache is also relaxed. OCMP is evaluated with the instruction level simulator developed by the authors. Two types of instruction level dispatching mechanisms are compared. The memory access mechanism is evaluated with various parameters such as memory access cost, the degree of simultaneous access to shared cache, and so on.

关键词： Processor scheduling Costs Multiprocessing systems Dispatching parallel processing Erbium Memory management Registers Delay

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An architecture-independent workload characterization model for parallel computer architectures

An architecture-independent workload characterization model ...

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Aizu international symposium on parallel algorithms/Architecture Synthesis

作者： A.I. Meajil T. El-Ghazawi T. Sterling Electrical Engineering & Computer Science Department George Washington University USA Center for Advanced Computing Research California Institute of Technology NASA Jet Propulsion Laboratory USA

A model is presented for representing and comparing workloads, based on the way they would exercise parallel machines. This workload characterization is derived from parallel instruction centroid and parallel workload similarity. The centroid is a simple measure that aggregates average parallelism instruction mix, and critical path length. When captured with abstracted information about communication requirements, the result is a powerful tool in understanding the requirements of workloads and their potential performance on target machines. The workload similarity is based on measuring the normalized Euclidean distance (ned) between workload centroids. It is shown that this workload representation method outperforms comparable ones in accuracy, as well as in time and space requirements. Analysis of the NAS parallel Benchmarks and their performance is presented to demonstrate some of the applications, such as performance prediction with good accuracy, and insight provided by this model.

关键词： Concurrent computing Computer architecture parallel processing Euclidean distance parallel architectures Design for experiments Benchmark testing Extraterrestrial measurements Multidimensional systems Propulsion

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A BSP approach to the scheduling of tightly-nested loops

A BSP approach to the scheduling of tightly-nested loops

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international symposium on parallel Processing

作者： R. Calinescu Oxford University Computing Laboratory Oxford UK

This paper addresses the scheduling of uniform-dependence loop nests within the framework of the bulk-synchronous parallel (BSP) model. Two broad classes of tightly-nested loops are identified in the paper and schedul... 详细信息

关键词： Processor scheduling Concurrent computing Costs parallel programming Laboratories parallel processing parallel architectures Code standards Phase change random access memory Encoding

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An efficient parallel algorithm for solving the knapsack problem on the hypercube

An efficient parallel algorithm for solving the knapsack pro...

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international symposium on parallel Processing

作者： A. Goldman D. Trystram Inst. de Mecanique de Grenoble Domaine Univ. France LMC-IMA Domaine Universitaire France

The authors present a new algorithm to solve the integral knapsack problem on the hypercube. The main idea is to use the fact that the precedence graph of the dynamic programming function of the knapsack problem is an irregular mesh. They propose a scheduling algorithm for irregular meshes on the hypercube. The efficiency of the algorithm is independent on the number of processors. They also present some improvements for the solution of the 0/1 knapsack problem on the hypercube.

关键词： parallel algorithms Hypercubes Dynamic programming Processor scheduling Approximation algorithms Scheduling algorithm Dynamic scheduling Art Concurrent computing Systolic arrays

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An object-oriented data cache architecture for programmable parallel digital signal processors

An object-oriented data cache architecture for programmable ...

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IEEE international Conference on algorithms and architectures for parallel Processing (ICAP)

作者： J. Kneip Laboratorium fir Informationstechnologie Universitat Hannover Hanover Germany

The paper describes concept and implementation of a data cache architecture with concurrent conflict free access to shared data for DSPs with parallel, synchronized processing units. It utilizes techniques known from object-oriented software design to achieve efficient and programmer friendly on-chip storage of data. The cache internally uses virtual 1D or 2D address spaces directly assigned to data structures instead of a conventional, linear address space. Data within the cache are distributed to a number of memory banks. Virtual local addresses are used for data location and hit/miss detection to minimize cost and memory latency. The object-oriented cache is fully transparent to programmer and compiler, reduces the amount of address calculations to be performed, exploits the 2D spatial locality typical for image processing algorithms and can be integrated into a standard RISC processor pipeline.

关键词： Computer architecture programming profession Digital signal processing Software design Data structures Costs Delay Program processors Image processing Reduced instruction set computing

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Design and evaluation of a submesh allocation scheme for two-dimensional mesh-connected parallel computers

Design and evaluation of a submesh allocation scheme for two...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： J.M. Chang Computer Engineering Program and Department of Computer Science Illinois Institute of Technology USA

This paper presents the design and evaluation of a novel submesh allocation algorithm called the Optimized Buddy System which is derived from conventional binary buddy system. Our scheme is made feasible by using a bit-map to represent the status of the processors. The proposed scheme can be mapped into hardware directly to take the advantage of the speed of a pure combinational-logic implementation. Although the buddy system may allocate a submesh that is much larger than the requested size, the logic that finds a free submesh can be augmented by a "bit-flipper" to relinquish the unused portion at the end of the submesh. This effectively eliminates internal fragmentation. The hardware complexity of proposed scheme (i.e. and-gate tree, or-gate tree and bit-flipper) is O(m/spl times/n), where m/spl times/n is the total number of the processors. The unique blind spot issue of proposed system is also investigated. Simulation results show that the allocation efficiency of the proposed scheme is similar to the one that uses best-fit approach.

关键词： Algorithm design and analysis Hardware Concurrent computing Very large scale integration Memory management Resource management Software algorithms Design engineering Computer science Design optimization

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Extraction and optimization of the implicit program parallelism by dynamic partial evaluation

Extraction and optimization of the implicit program parallel...

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Aizu international symposium on parallel algorithms/Architecture Synthesis

作者： A. Tchernykh A. Stepanov A. Lupenko N. Tchernykh Comput. Sci. Dept. CICESE Ensenada Mexico Russian Academy of Science Moscow Russia

Much work has been done to implement declarative languages in parallel form. Most of them tend to resort to imperative features for some purposes, particularly for description of the parallelism. We propose parallel computation on associative networks, a machine independent parallel programming model, for automatic extraction of available inherent parallelism and optimization of declarative programs. Associative networks are used for representing program-like and data-like information. The computation follows the transformation style of information processing. All computational mechanisms are oriented reward the processing incomplete information and perform parallel partial evaluation. This partial evaluation is a base of the proposed technique for automatic transforming, optimizing, and parallelizing declarative programs.

关键词： parallel processing Computer networks Concurrent computing Data mining Runtime parallel programming Computational modeling High performance computing Computer science Information processing

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