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检索条件"任意字段=International Symposium on Parallel Architectures, Algorithms, and Programming"

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Extraction and optimization of the implicit program parallelism by dynamic partial evaluation

Extraction and optimization of the implicit program parallel...

引用

Aizu international symposium on parallel algorithms/Architecture Synthesis

作者： A. Tchernykh A. Stepanov A. Lupenko N. Tchernykh Comput. Sci. Dept. CICESE Ensenada Mexico Russian Academy of Science Moscow Russia

Much work has been done to implement declarative languages in parallel form. Most of them tend to resort to imperative features for some purposes, particularly for description of the parallelism. We propose parallel computation on associative networks, a machine independent parallel programming model, for automatic extraction of available inherent parallelism and optimization of declarative programs. Associative networks are used for representing program-like and data-like information. The computation follows the transformation style of information processing. All computational mechanisms are oriented reward the processing incomplete information and perform parallel partial evaluation. This partial evaluation is a base of the proposed technique for automatic transforming, optimizing, and parallelizing declarative programs.

关键词： parallel processing Computer networks Concurrent computing Data mining Runtime parallel programming Computational modeling High performance computing Computer science Information processing

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A high-level cellular programming model for massively parallel processing

A high-level cellular programming model for massively parall...

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international Workshop on High-Level parallel programming Models and Supportive Environments

作者： G. Spezzano D. Talia ISI-CNR DEIS Universitá della Calabria Rende Italy

Cellular automata are used for designing high performance applications in many areas. The paper describes CARPET, a high level programming language based on the cellular automata model. CARPET is a programming language designed to support the development of parallel high performance software. It exploits the computing power of a highly parallel computer releasing a user from using explicit parallel constructs. A CARPET implementation has been used for programming cellular algorithms in the CAMEL parallel environment. With CARPET, a user might write programs to describe the actions of thousands of simple active agents interacting locally, then the CAMEL environment allows a user to observe the global complex evolution that arises from their parallel execution and their local interactions.

关键词： parallel programming parallel processing Concurrent computing Lattices Application software Computer languages Computational modeling Computer architecture parallel architectures High level languages

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A parallel pipelined renderer for time-varying volume data

A parallel pipelined renderer for time-varying volume data

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Tzi-Cier Chiueh Kwan-Liu Ma Computer Science Department State University of New York Stony Brook Stony Brook NY USA NASA Langley Research Center Institute for Computer Applications in Science and Engineering Hampton VA USA

ISBN: (纸本)0818682596

This paper presents a strategy for efficiently rendering time-varying volume data on a distributed-memory parallel computer. Visualizing time-varying volume data take both large storage space and long computation time. Instead of employing all processors to render one volume at a time, a pipelined rendering approach partitions processors into groups so that multiple volumes can be rendered concurrently. The overall rendering time is greatly minimized because rendering is overlapped with I/O required to load the volume data sets. Moreover, parallelization overhead may be reduced as a result of partitioning the processors. We modify an existing parallel volume renderer to exploit various levels of rendering parallelism and to study how the partitioning of processors may lead to optimal rendering performance. We find that two factors affecting the overall execution time are resource utilization efficiency and pipeline startup latency. The optimal partitioning configuration is the one that balances these two factors. Tests on Intel Paragon computers show that in general optimal partitionings do exist for a given rendering task and result in 40-50% saving in overall rendering time.

关键词： parallel processing Animation NASA Delay Computer applications Data engineering Concurrent computing Data visualization Rendering (computer graphics) Computer science

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A comparison of general approaches to multiprocessor scheduling

A comparison of general approaches to multiprocessor schedul...

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international symposium on parallel Processing

作者： Jing-Chiou Liou M.A. Palis AT and T Laboratories Middletown NJ USA Department of Computer Science Rutgers University Camden NJ USA

The paper demonstrates the effectiveness of the two phase method of scheduling, in which task clustering is performed prior to the actual scheduling process. Task clustering determines the optimal or near optimal number of processors on which to schedule the task graph. In other words, there is never a need to use more processors (even though they are available) than the number of clusters produced by the task clustering algorithm. The paper also indicates that when task clustering is performed prior to scheduling, load balancing (LB) is the preferred approach for cluster merging. LB is fast, easy to implement, and produces significantly better final schedules than communication traffic minimizing (CTM). In summary, the two phase method consisting of task clustering and load balancing is a simple, yet highly effective strategy for scheduling task graphs on distributed memory parallel architectures.

关键词： Processor scheduling Clustering algorithms Scheduling algorithm Merging Software algorithms Load management Optimizing compilers Laboratories Computer science parallel architectures

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A new general purpose parallel database system

A new general purpose parallel database system

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： M. Afshar J. Bates G. Bierman K. Moody Computer Laboratory University of Cambridge Cambridge UK

This paper is concerned with the transparent parallelisation of declarative database queries, based on theoretical principles. We have designed an entire database architecture suitable for use on any general-purpose parallel machine. This architecture addresses the shortcomings in flexibility and scalability of commercial parallel databases. A substantial benefit is that the mathematical principles underlying our framework allow provably correct parallel evaluations and optimisations, using compile-time transformations. We address parallelism in a language-independent way through the choice of monoids as a formulation for expressing and modelling queries. Queries expressed in our declarative language are transformed into applications of a higher-order function, the monoid homomorphism. The evaluation of this function is partitioned at run-time, giving a tree-like processor topology, the depth and breadth of which can be varied with a declarative execution plan. Leaf nodes within the evaluation tree operate on their own data partitions and forward results to the appropriate interior nodes. Due to the nature of our language, the functions that are necessary to combine results from independent parallel evaluations are generated automatically at compile-time from a monoid definition dictionary, additions to which can be made to extend the system's data types. We have built a complete prototype of our system, which uses Swiss Radio Corporation's entire recorded music catalogue, on a general-purpose Ar1000, 128-cell parallel computer at the IFPC.

关键词： Database systems Computer architecture parallel processing Prototypes Transaction databases Laboratories parallel machines Scalability Runtime Concurrent computing

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SCL-Chan: an asynchronous data-parallel language for irregular algorithms

SCL-Chan: an asynchronous data-parallel language for irregul...

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international Workshop on High-Level parallel programming Models and Supportive Environments

作者： E. Melin B. Raffin X. Rebeuf B. Virot LIFO IIIA Université dE28099Orléans Orleans France

parallelism suffers from a lack of programming languages both simple to handle and able to take advantage of the power of present parallel computers. If parallelism expression is too high level, compilers have to perform complex optimizations leading often to poor performances. One the other hand, too low level parallelism transfers difficulties toward the programmer. We propose a programming language that integrates both a synchronous data parallel programming model and an asynchronous execution model. The synchronous data parallel programming model allows safe program design. The asynchronous execution model yields an efficient execution on present MIMD architectures without any program transformation. Our language relies an logical instruction ordering exploited by specific send/receive communications. It allows one to express only the effective data dependences between processors. This ability is enforced by a possible send/receive unmatching, useful for irregular algorithms. A sparse vector computation exemplifies our language potentialities.

关键词： parallel processing Concurrent computing parallel programming programming profession Optimizing compilers Computer languages System recovery Communication system control Computer architecture Algorithm design and analysis

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Analysis of several scheduling algorithms under the nano-threads programming model

Analysis of several scheduling algorithms under the nano-thr...

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international symposium on parallel Processing

作者： X. Martorell J. Labarta N. Navarro E. Ayguade Departament d'Arquitectura de Computadors Universitat Poliltècnica de Catalunya Barcelona Spain

The authors present the analysis, in a dynamic processor allocation environment, of four scheduling algorithms running on top of the nano-threads programming model. Three of them are well-known: uniform-sized chunking, guided self-scheduling and trapezoid self-scheduling. The fourth is their proposal: adaptable size chunking. In that environment, applications are automatically decomposed into tasks by a parallelizing compiler which uses the hierarchical task graph to represent the source application. The parallel code is an executable representation of this graph with the support of a user-level library (the nano-threads library). The execution environment includes a user-level process (CPU manager) which controls the allocation of processors to applications. The analysis of the scheduling algorithms shows it is possible to provide enough information to the library to allow a fast adaptation to dynamic changes in the processors allocated to the application.

关键词： Algorithm design and analysis Scheduling algorithm Libraries Dynamic programming Job shop scheduling Processor scheduling Dynamic scheduling Proposals Environmental management Yarn

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A randomized sorting algorithm on the BSP model

A randomized sorting algorithm on the BSP model

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international symposium on parallel Processing

作者： A.V. Gerbessiotis C.J. Siniolakis Computing Laboratory Oxford University UK

The authors present a new randomized sorting algorithm on the bulk-synchronous parallel (BSP) model. The algorithm improves upon the parallel slack of previous algorithms to achieve optimality. Tighter probabilistic bounds are also established. It uses sample sorting and utilizes recently introduced search algorithms for a class of data structures on the BSP model. Moreover the methods are within a 1+o(1) multiplicative factor of the respective sequential methods in terms of speedup for a wide range of the BSP parameters.

关键词： Sorting Computer networks Communication networks Throughput Concurrent computing Laboratories Data structures parallel programming parallel processing Computer architecture

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Memory hierarchy design for Jetpipeline: to execute scalar and vector instructions in parallel

Memory hierarchy design for Jetpipeline: to execute scalar a...

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Aizu international symposium on parallel algorithms/Architecture Synthesis

作者： T. Sasaki T. Nakaike K. Takano M. Katahira H. Kobayashi T. Nakamura Graduate School of Information Sciences University of Tohoku Sendai Japan

Superscalar and VLIW architectures are based on instruction level parallelism (ILP), which ideally achieve high performance to execute multiple instructions in parallel. However, the system performance is restricted because of the Von Neumann bottleneck. Therefore, the memory hierarchy design is very important in this kind of architecture. We have proposed a computer architecture named Jetpipeline, which can execute both vector and scalar instructions in parallel. To make full use of the computing ability of Jetpipeline, the paper presents the memory hierarchy design for Jetpipeline and evaluates the effect of the design on the system performance of Jetpipeline through simulations.

关键词： Computer architecture parallel processing Dynamic scheduling Clocks Computer aided instruction Pipelines Processor scheduling System performance Computational modeling Business

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Global synchronization of asynchronous arrays

Global synchronization of asynchronous arrays

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Aizu international symposium on parallel algorithms/Architecture Synthesis

作者： V. Varshavsky V. Marakhovsky University of Aizu Aizu-Wakamatsu Japan

The problem of global synchronization in massively parallel systems is discussed for the level of models represented by asynchronous cellular automata arrays. Synchronization is called global if a given asynchronous automata array functions in logical time so that its behavior can be homomorphously mapped to the behavior of the prototype synchronous system in physical time. Our approach is decomposing the asynchronous array to synchro-stratum which acts as a distributed asynchronous clock and automata stratum whose automata have a construction similar to that of the synchronous prototype array automata. For various disciplines of prototype synchronization, the corresponding variants of synchro-stratum implementation for the asynchronous analogue are discussed.

关键词： Logic arrays Synchronization Clocks Hardware Automata Prototypes Software prototyping Signal processing Encyclopedias parallel programming

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