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检索条件"任意字段=International Symposium on Parallel Architectures, Algorithms, and Programming"

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Prefetching by self-contained variables-a generalization from array to recursive data structures

Prefetching by self-contained variables-a generalization fro...

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Aizu international symposium on parallel algorithms/Architecture Synthesis

作者： Wai-Wai Chan Chi-Hung Chi National University of Singapore Singapore SG

ISBN: (纸本)0818678704

Data prefetching has proven to be effective in hiding memory latency from the program execution time. Most current data prefetching schemes are targeted only for array references with constant strides; for array references with non-constant strides, they lose most of their effectiveness. In this paper, we propose a novel data prefetching scheme, based on a property called the self-containedness of variables, which is widely available in most loop-rich applications. We observed that the update pattern of a self-contained variable in a loop can be accurately predicted. The predicated value can then be used for accurate data prefetching if the variable is the only loop-variant component of an address expression in a memory access instruction. With suitable hardware support, this scheme can be used to prefetch data from recursive data structures in additional to array elements. Moreover, the coverage of this scheme is highly selectable. It can be customized easily to fit the cost-performance requirements of different processors that are designed for different applications.

关键词： Prefetching Data structures High level languages Delay Information systems Computer science Hardware programming profession Program processors Reduced instruction set computing

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A specific compilation scheme for image processing architecture

A specific compilation scheme for image processing architect...

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Computer architectures for Machine Perception (CAMP)

作者： F. Bodin H. Essafi M. Pic IRISA-INRI Rennes France LETI (CEA Technologies Avancees) Gif-sur-Yvette France

This paper presents a compilation scheme for a high-level programming environment C/sub T//sup +/+ that allows to obtain good performance at a low engineering cost. C/sub T//sup +/+ is based on C++ and has been designed to easily develop algorithms on multi-SIMD parallel computers. We compare our implementation mechanism with others and show that it produces efficient code for low and intermediate level image processing algorithms. The first target architecture is the SYMPHONIE image processing architecture developed at LETI.

关键词： Image processing Concurrent computing Computer architecture Libraries Software standards Iris programming environments Computed tomography Costs Algorithm design and analysis

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An approach to fault-tolerant parallel processing on intermittently idle, heterogeneous workstations

An approach to fault-tolerant parallel processing on intermi...

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international symposium on Fault-Tolerant Computing (FTCS)

作者： K. Jeong D. Shasha S. Talla P. Wyckoff Laboratory for Nuclear Studies Cornell University Ithaca NY USA Department of Computer Science New York University New York NY USA

We propose a novel approach to harness the idle cycles of workstations connected by LAN/WANs for long running scientific computations and present performance results for our prototype system called Persistent Linda (PLinda). PLinda offers low runtime overhead and, migration among heterogeneous architectures while retreating quickly when owners return to their workstations. PLinda achieves this by implementing a lightweight transaction model that lacks serializability and durability, but preserves a basic guarantee: if a PLinda execution terminates, it has the same result as some failure-free Linda execution. Further, by storing the state of a PLinda process as a set of core variables as of each transaction commit, a PLinda process can migrate among different architectures. Within the space of lightweight transaction models, we offer three mechanisms that make different tradeoffs between failure-free performance and recovery time. All three mechanisms may be used at the same time in a single application; each process using the mechanism which is best suited for its characteristics. Our experiments illustrate the tradeoffs of the three mechanisms as well as the overall performance of the system on applications from physics and finance.

关键词： Fault tolerance parallel processing Workstations Fault tolerant systems Concurrent computing Runtime Physics parallel programming Laboratories Computer science

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Improved signal processing with dynamic recurrent neural models using ARMA-like units

Improved signal processing with dynamic recurrent neural mod...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： J.-P. Draye D. Pavisic G. Cheron G. Libert Parallel Information Processing Laboratory Polytechnical Faculty of Mons Mons Belgium Laboratory of Biomechanics Free University of Brussels Brussels Belgium

We have shown that dynamic recurrent neural networks with ARMA-like units can tackle the problem of complex signal processing. In some cases of very highly nonlinear processing, their use can even be inevitable. We have shown that the Pontryagin Maximum Principle (from the theory of control) helps to elegantly derive the continuous-time learning algorithms for these complex neural architectures Finally, we have presented practical biomedical application where dynamic recurrent networks exhibit, their robustness. We are currently investigating other applications in the field of mathematics (such as interpolation tasks i.e., for the forecasting of stock market value) and of engineer.

关键词： Signal processing Biomedical signal processing Signal processing algorithms Recurrent neural networks Robust control Mathematics Interpolation Economic forecasting Stock markets Biomedical engineering

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A simple parallel architecture for discrete wavelet transform

A simple parallel architecture for discrete wavelet transfor...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Si-Jung Chang Moon Ho Lee Jin-Jong Cha Department of Information & Communications Engineering Chonbuk National University of Korea South Korea Electronics and Telecommnications Research Institute Taejon South Korea

In this paper, we present a simple parallel architecture for Discrete Wavelet Transform (DWT). Efficient computation of the pyramid algorithm for the computing of the discrete wavelet transform is possible due to the similarity between computation results of each octave. By using similarity, we separated the filter into 2 parts, an even filter and an odd filter. 1 octave and other octave computation are performed in the even and odd filters at the same time. The proposed architecture has following features. (1) Critical path is 1 multiplier and 1 adder; (2) the number of required registers is 1+J*([L/sub h//2]-1)+1+J*([L/sub 1//2]-1)+J, where J is the number of octaves, L/sub h/ is length of the highpass filter and L/sub 1/ is length of the lowpass filter.

关键词： Discrete wavelet transforms parallel architectures Filters Signal processing Frequency Signal processing algorithms Filtering Telecommunication computing Computer architecture Wavelet transforms

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View Caching: efficient software shared memory for dynamic computations

View Caching: efficient software shared memory for dynamic c...

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international symposium on parallel Processing

作者： V. Karamcheti A.A. Chien Department of Computer Science University of Illinois Urbana-Champaign USA

Software distributed shared memory (DSM) techniques, while effective on applications with coarse-grained sharing, yield poor performance for the fine-grained sharing encountered in applications increasingly relying on sophisticated adaptive and hierarchical algorithms. Such applications exhibit irregular communication patterns unsynchronized with computation, incurring large overheads for synchronous (request-reply) DSM protocols that require responsive processing of coherence messages. We describe a new DSM framework, View Caching, that addresses this problem by utilizing application knowledge of data access semantics to enable the construction of low-overhead, asynchronous coherence protocols. Experiments on the Gray T3D show that view caching enables efficient execution of fine-grained irregular applications, reducing both coherence overheads and idle time to improve performance by up to 35% over a weakly-consistent DSM implementation.

关键词： Access protocols Coherence Delay Application software Hardware Software performance Dynamic programming Runtime Robustness Computer science

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Interprocedural Distribution Assignment Placement: More Than Just Enhancing Intraprocedural Placing Techniques 97

Interprocedural Distribution Assignment Placement: More Than...

引用

Proceedings of the 1997 international Conference on parallel architectures and Compilation Techniques

作者： J. Knoop E. Mehofer

ISBN: (纸本)9780818680908

Avoiding unnecessary remappings at run-time by means of a strategic distribution assignment placement (DAP) is a major means for improving the run-time efficiency of data-parallel programs on distributed-memory architectures. In Proc. Euro-Par '97, pp. 364-73 (1997), we presented a novel and aggressive intraprocedural algorithm achieving this by eliminating partially redundant and partially dead distribution assignments. In this paper, we show how to enhance this approach interprocedurally. Surprisingly at first sight, it turns out that a straightforward adaption of the intraprocedural approach fails because central properties being valid for the intraprocedural case do not carry over to the interprocedural one, revealing severe anomalies. After discussing the essential differences and analogies of DAP in the interprocedural and interprocedural cases, we show how to overcome these anomalies in order to arrive at a powerful and flexible approach for interprocedural DAP (IDAP). As in the interprocedural case, we get a hierarchy of IDAP algorithms of varying power and efficiency supporting user-customized solutions. First practical experiences underline its importance and effectivity.

关键词： unnecessary run-time remappings optimization dynamic data redistribution intraprocedural placing techniques run-time efficiency anomalies partially redundant distribution assignment elimination data-parallel programs High Performance Fortran user-customized solutions parallel programming interprocedural data-flow analysis algorithm hierarchy partially dead distribution assignment elimination interprocedural distribution assignment placement distributed-memory architectures

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A parallel Algorithm For Compile-Time Scheduling Of parallel Programs On Multiprocessors 97

A Parallel Algorithm For Compile-Time Scheduling Of Parallel...

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Proceedings of the 1997 international Conference on parallel architectures and Compilation Techniques

作者： Yu-Kwong Kwok I. Ahmad

ISBN: (纸本)9780818680908

Proposes a parallel randomized algorithm, called PFAST (parallel Fast Assignment using Search Technique), for scheduling parallel programs represented by directed acyclic graphs (DAGs) during compile-time. The PFAST algorithm has O(e) time complexity, where e is the number of edges in the DAG. This linear-time algorithm works by first generating an initial solution and then refining it using a parallel random search. Using a prototype computer-aided parallelization and scheduling tool called CASCH (Computer-Aided SCHeduling), the algorithm is found to outperform numerous previous algorithms while taking dramatically smaller execution times. The distinctive feature of this research is that, instead of simulations, our proposed algorithm is evaluated and compared with other algorithms using the CASCH tool with real applications running on an Intel Paragon. The PFAST algorithm is also evaluated with randomly generated DAGs for which optimal schedules are known. The algorithm generated optimal solutions for a majority of the test cases and close-to-optimal solutions for the others. The proposed algorithm is the fastest scheduling algorithm known to us and is an attractive choice for scheduling under running time constraints.

关键词： Intel Paragon parallel fast assignment parallel random search technique execution times compile-time scheduling CASCH tool time complexity running time constraints multiprocessors parallel programs directed acyclic graphs PFAST algorithm computer-aided scheduling tool parallel programming parallel randomized algorithm linear-time algorithm computer-aided parallelization

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Simulated evolution based code generation for programmable DSP processors

Simulated evolution based code generation for programmable D...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Yin-Tsung Hwang Jer-Sho Hwang Department of Electronic Engineering National Yunlin Institute of Technology Yunlin Taiwan

Modern DSP processors are capable of performing multiple instructions concurrently. Due to the limitation in internal structure, parallel instructions often impose constraints on the operand data types. In this paper, we propose a novel code generation method which takes both operand data type assignment and instruction scheduling problems into account. The operand data types can be adjusted during instruction scheduling to create more parallel instructions. A simulated evolution based iterative scheduling algorithm is devised to solve the operand data type assignment, instruction scheduling and register allocation problems in one. Tested benchmark programs indicate that our method can generate very efficient codes in all cases.

关键词： Digital signal processing Registers Processor scheduling Scheduling algorithm Clocks Arithmetic Benchmark testing Iterative methods Iterative algorithms Dynamic programming

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Oblivious routing algorithms on the mesh of buses

Oblivious routing algorithms on the mesh of buses

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international symposium on parallel Processing

作者： K. Iwama E. Miyano Department of Computer Science and Communication Engineering Kyushu University Fukuoka Japan Kyushu Daigaku Fukuoka JP

An optimal [1.5N/sup 1/2/] lower bound is shown for oblivious routing on the mesh of buses, a two-dimensional parallel model consisting of N/sup 1/2//spl times/N/sup 1/2/ processors, N/sup 1/2/ row and N/sup 1/2/ column buses but no local connections between neighbouring processors. Many lower bound proofs for routing on mesh-structured models use a single instance (adversary) which includes difficult packet-movement. This approach does not work in our case; our proof is the first which exploits the fact that the routing algorithm has to cope with many different instances. Note that the two-dimensional mesh of buses includes 2N/sup 1/2/ buses and each processor can access two different buses. Apparently the three-dimensional model provides more communication facilities, namely, including 3N/sup 2/3/ buses and each processor can access three different buses. Surprisingly, however, the oblivious routing on the three-dimensional mesh of buses needs more time, i.e., /spl Omega/(N/sup 2/3/) steps, which is another important result of this paper.

关键词： Routing Computer science parallel architectures Scalability Computer architecture Concurrent computing Upper bound Hypercubes

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