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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Si-Jung Chang Moon Ho Lee Jin-Jong Cha Department of Information & Communications Engineering Chonbuk National University of Korea South Korea Electronics and Telecommnications Research Institute Taejon South Korea

In this paper, we present a simple parallel architecture for Discrete Wavelet Transform (DWT). Efficient computation of the pyramid algorithm for the computing of the discrete wavelet transform is possible due to the similarity between computation results of each octave. By using similarity, we separated the filter into 2 parts, an even filter and an odd filter. 1 octave and other octave computation are performed in the even and odd filters at the same time. The proposed architecture has following features. (1) Critical path is 1 multiplier and 1 adder; (2) the number of required registers is 1+J*([L/sub h//2]-1)+1+J*([L/sub 1//2]-1)+J, where J is the number of octaves, L/sub h/ is length of the highpass filter and L/sub 1/ is length of the lowpass filter.

关键词： Discrete wavelet transforms parallel architectures Filters Signal processing Frequency Signal processing algorithms Filtering Telecommunication computing Computer architecture Wavelet transforms

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View Caching: efficient software shared memory for dynamic computations

View Caching: efficient software shared memory for dynamic c...

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international symposium on parallel Processing

作者： V. Karamcheti A.A. Chien Department of Computer Science University of Illinois Urbana-Champaign USA

Software distributed shared memory (DSM) techniques, while effective on applications with coarse-grained sharing, yield poor performance for the fine-grained sharing encountered in applications increasingly relying on sophisticated adaptive and hierarchical algorithms. Such applications exhibit irregular communication patterns unsynchronized with computation, incurring large overheads for synchronous (request-reply) DSM protocols that require responsive processing of coherence messages. We describe a new DSM framework, View Caching, that addresses this problem by utilizing application knowledge of data access semantics to enable the construction of low-overhead, asynchronous coherence protocols. Experiments on the Gray T3D show that view caching enables efficient execution of fine-grained irregular applications, reducing both coherence overheads and idle time to improve performance by up to 35% over a weakly-consistent DSM implementation.

关键词： Access protocols Coherence Delay Application software Hardware Software performance Dynamic programming Runtime Robustness Computer science

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Interprocedural Distribution Assignment Placement: More Than Just Enhancing Intraprocedural Placing Techniques 97

Interprocedural Distribution Assignment Placement: More Than...

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Proceedings of the 1997 international Conference on parallel architectures and Compilation Techniques

作者： J. Knoop E. Mehofer

ISBN: (纸本)9780818680908

Avoiding unnecessary remappings at run-time by means of a strategic distribution assignment placement (DAP) is a major means for improving the run-time efficiency of data-parallel programs on distributed-memory architectures. In Proc. Euro-Par '97, pp. 364-73 (1997), we presented a novel and aggressive intraprocedural algorithm achieving this by eliminating partially redundant and partially dead distribution assignments. In this paper, we show how to enhance this approach interprocedurally. Surprisingly at first sight, it turns out that a straightforward adaption of the intraprocedural approach fails because central properties being valid for the intraprocedural case do not carry over to the interprocedural one, revealing severe anomalies. After discussing the essential differences and analogies of DAP in the interprocedural and interprocedural cases, we show how to overcome these anomalies in order to arrive at a powerful and flexible approach for interprocedural DAP (IDAP). As in the interprocedural case, we get a hierarchy of IDAP algorithms of varying power and efficiency supporting user-customized solutions. First practical experiences underline its importance and effectivity.

关键词： unnecessary run-time remappings optimization dynamic data redistribution intraprocedural placing techniques run-time efficiency anomalies partially redundant distribution assignment elimination data-parallel programs High Performance Fortran user-customized solutions parallel programming interprocedural data-flow analysis algorithm hierarchy partially dead distribution assignment elimination interprocedural distribution assignment placement distributed-memory architectures

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A parallel Algorithm For Compile-Time Scheduling Of parallel Programs On Multiprocessors 97

A Parallel Algorithm For Compile-Time Scheduling Of Parallel...

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Proceedings of the 1997 international Conference on parallel architectures and Compilation Techniques

作者： Yu-Kwong Kwok I. Ahmad

ISBN: (纸本)9780818680908

Proposes a parallel randomized algorithm, called PFAST (parallel Fast Assignment using Search Technique), for scheduling parallel programs represented by directed acyclic graphs (DAGs) during compile-time. The PFAST algorithm has O(e) time complexity, where e is the number of edges in the DAG. This linear-time algorithm works by first generating an initial solution and then refining it using a parallel random search. Using a prototype computer-aided parallelization and scheduling tool called CASCH (Computer-Aided SCHeduling), the algorithm is found to outperform numerous previous algorithms while taking dramatically smaller execution times. The distinctive feature of this research is that, instead of simulations, our proposed algorithm is evaluated and compared with other algorithms using the CASCH tool with real applications running on an Intel Paragon. The PFAST algorithm is also evaluated with randomly generated DAGs for which optimal schedules are known. The algorithm generated optimal solutions for a majority of the test cases and close-to-optimal solutions for the others. The proposed algorithm is the fastest scheduling algorithm known to us and is an attractive choice for scheduling under running time constraints.

关键词： Intel Paragon parallel fast assignment parallel random search technique execution times compile-time scheduling CASCH tool time complexity running time constraints multiprocessors parallel programs directed acyclic graphs PFAST algorithm computer-aided scheduling tool parallel programming parallel randomized algorithm linear-time algorithm computer-aided parallelization

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Simulated evolution based code generation for programmable DSP processors

Simulated evolution based code generation for programmable D...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Yin-Tsung Hwang Jer-Sho Hwang Department of Electronic Engineering National Yunlin Institute of Technology Yunlin Taiwan

Modern DSP processors are capable of performing multiple instructions concurrently. Due to the limitation in internal structure, parallel instructions often impose constraints on the operand data types. In this paper, we propose a novel code generation method which takes both operand data type assignment and instruction scheduling problems into account. The operand data types can be adjusted during instruction scheduling to create more parallel instructions. A simulated evolution based iterative scheduling algorithm is devised to solve the operand data type assignment, instruction scheduling and register allocation problems in one. Tested benchmark programs indicate that our method can generate very efficient codes in all cases.

关键词： Digital signal processing Registers Processor scheduling Scheduling algorithm Clocks Arithmetic Benchmark testing Iterative methods Iterative algorithms Dynamic programming

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Oblivious routing algorithms on the mesh of buses

Oblivious routing algorithms on the mesh of buses

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international symposium on parallel Processing

作者： K. Iwama E. Miyano Department of Computer Science and Communication Engineering Kyushu University Fukuoka Japan Kyushu Daigaku Fukuoka JP

An optimal [1.5N/sup 1/2/] lower bound is shown for oblivious routing on the mesh of buses, a two-dimensional parallel model consisting of N/sup 1/2//spl times/N/sup 1/2/ processors, N/sup 1/2/ row and N/sup 1/2/ column buses but no local connections between neighbouring processors. Many lower bound proofs for routing on mesh-structured models use a single instance (adversary) which includes difficult packet-movement. This approach does not work in our case; our proof is the first which exploits the fact that the routing algorithm has to cope with many different instances. Note that the two-dimensional mesh of buses includes 2N/sup 1/2/ buses and each processor can access two different buses. Apparently the three-dimensional model provides more communication facilities, namely, including 3N/sup 2/3/ buses and each processor can access three different buses. Surprisingly, however, the oblivious routing on the three-dimensional mesh of buses needs more time, i.e., /spl Omega/(N/sup 2/3/) steps, which is another important result of this paper.

关键词： Routing Computer science parallel architectures Scalability Computer architecture Concurrent computing Upper bound Hypercubes

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A graph-theoretic sufficient condition for FPGA/FPIC switch-module routability

A graph-theoretic sufficient condition for FPGA/FPIC switch-...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Yao-Wen Chang D.F. Wong C.K. Wong Department of Computer and Information Science National Chiao Tung University Hsinchu Taiwan Department of Computer Sciences University of Texas Austin Austin TX USA Department of Computer Science Chinese University of Hong Kong Hong Kong China

Switch modules are the most important component of the routing resources in FPGAs/FPICs. We consider in this paper an FPGA/FPIC switch-module analyse's problem: The inputs consist of a switch-module description and the number of nets required to be routed through the switch module; the question is to determine if there exists a feasible routing for the routing requirements on the switch module. This problem is applicable to the routability evaluation of FPGA/FPIC switch modules, the switch-module design for FPGAs/FPICs, and FPGA/FPIC routing. We present a graph-theoretic sufficient condition for the analyse's problem. The implications of the condition are: (1) there exist several classes of efficient approximation algorithms for the analysis problem; (2) there exist several classes of switch-module architectures on which the analysis problem can be solved efficiently.

关键词： Sufficient conditions Field programmable gate arrays Switches Routing Logic circuits Logic programming Integrated circuit interconnections Algorithm design and analysis Logic arrays Pins

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MediaBench: a tool for evaluating and synthesizing multimedia and communications systems 30

MediaBench: a tool for evaluating and synthesizing multimedi...

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IEEE/ACM international symposium on Microarchitecture (MICRO)

作者： Chunho Lee M. Potkonjak W.H. Mangione-Smith The Departments of Computer Science University of California Los Angeles USA The Departments of Computer Science and Electrical Engineering University of California Los Angeles USA

ISBN: (纸本)9780818679773

Significant advances have been made in compilation technology for capitalizing on instruction-level parallelism (ILP). The vast majority of ILP compilation research has been conducted in the context of general-purpose computing, and more specifically the SPEC benchmark suite. At the same time, a number of microprocessor architectures have emerged which have VLIW and SIMD structures that are well matched to the needs of the ILP compilers. Most of these processors are targeted at embedded applications such as multimedia and communications, rather than general-purpose systems. Conventional wisdom, and a history of hand optimization of inner-loops, suggests that ILP compilation techniques are well suited to these applications. Unfortunately, there currently exists a gap between the compiler community and embedded applications developers. This paper presents MediaBench, a benchmark suite that has been designed to fill this gap. This suite has been constructed through a three-step process: intuition and market driven initial selection, experimental measurement to establish uniqueness, and integration with system synthesis algorithms to establish usefulness.

关键词： Multimedia communication Multimedia systems Computer architecture Application software parallel processing Microprocessors VLIW Program processors Pipeline processing Digital signal processing

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Proceedings of the 1996 2nd international symposium on parallel architectures, algorithms, and Networks, I-SPAN

Proceedings of the 1996 2nd International Symposium on Paral...

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Proceedings of the 1996 2nd international symposium on parallel architectures, algorithms, and Networks, I-SPAN

The proceedings contains 92 papers from the 1996 international symposium on parallel architectures, algorithms and Networks. Topics discussed include: massively parallel processors;distributed memory parallel computers;multistage interconnection networks;Banyan switching fabrics;internetworking;transmission control protocol/Internet protocol networks;train traffic and event driven simulations;universal broadband network access devices;customer premises networks;and parallel random access machines.

关键词： parallel processing systems

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Scalability, portability and predictability: The BSP approach to parallel programming

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FUTURE GENERATION COMPUTER SYSTEMS 1996年第4期12卷 265-272页

作者： McColl, WF Programming Research Group Oxford University Computing Laboratory Wolfson Building Parks Road Oxford OX1 3QD UK

General purpose parallel computing systems come in a variety of forms. We have various kinds of distributed memory architectures, shared memory multiprocessors, and clusters of workstations. New technologies may increase this range still further. Can one hope to design portable and scalable parallel software in the face of such architectural diversity? In this paper we show that it is indeed possible to produce fully portable parallel software which will run with highly efficient, scalable and predictable performance on any general purpose parallel architecture. The approach we describe is based on the bulk synchronous parallel (BSP) model of computation. The BSP model provides a simple, unified framework for the design and programming of all kinds of general purpose parallel systems. Over the last few years, a number of important research activities in algorithms and architectures have been pursued as part of this new approach to scalable parallel computing. In this paper we give some simple BSP algorithms and show how they can be expressed as programs. We also briefly describe some of the BSP programming language developments which are now being pursued.

关键词： parallel computing bulk synchronous parallel model programming languages parallel algorithms

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