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检索条件"任意字段=International Symposium on Parallel Architectures, Algorithms, and Programming"

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Design and implementation of a high speed parallel architecture for ATM UNI

Design and implementation of a high speed parallel architect...

引用

international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Wen-Yu Tseng Chin-Chou Chen D.S.L. Wei Sy-Yen Kuo Department of Electrical Engineering National Taiwan University Taipei Taiwan School of Computer Science and Engineering University of Aizu Fukushima Japan

In this paper, a parallel architecture is proposed to support the operations described in the ITU-T Recommendation I.432 (B-ISDN user-network interface-Physical layer specification). It is rather difficult to perform their operations on a bit serial architecture at a high rate. This paper demonstrates how these tasks can be achieved by means of parallelism. First, we describe the user-network interfaces in general and their physical layer properties. Then a parallel architecture is proposed with a general translation method which converts the serial operation into the parallel one. The application of the parallel architecture on each function is also depicted and the system has been realized in hardware using CMOS technology.

关键词： parallel architectures Asynchronous transfer mode CMOS technology Bit rate B-ISDN Physical layer Network interfaces Frequency Computer science Design engineering

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Efficient in-place sorting algorithms using feasible parallel machine models

Efficient in-place sorting algorithms using feasible paralle...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： S.Q. Zheng B. Calidas Yanjung Zhang Department of Computer Science Louisiana State University Baton Rouge LA USA Department of Electrical and Computer Engineering Louisiana State University Baton Rouge LA USA Department of Computer Science and Engineering Southern Methodist University Dallas TX USA

We present a simple and general parallel sorting scheme, ZZ-sort, which can be used to derive a class of efficient in-place sorting algorithms on realistic parallel machine models. We prove a tight bound for the worst case performance of ZZ-sort. We also demonstrate the average performance of ZZ-sort by experimental results obtained on a MasPar parallel computer. Our experiments indicate that ZZ-sort can be incorporated into a distributed memory parallel computer system as a standard routine, and this routine is useful for space critical situations. Finally, we show that ZZ-sort can be used to convert a non-adaptive parallel sorting algorithm into an in-place and adaptive one by considering the problem of sorting an arbitrarily large input on fixed-size reconfigurable meshes.

关键词： Sorting parallel machines Application software Concurrent computing Memory management Computer science Power engineering computing parallel processing Power engineering and energy Data communication

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On parallelization of neural classification algorithms

On parallelization of neural classification algorithms

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： K.P. Lam A. Furness Automatic Identification Research and Teaching Laboratory Electronic Engineering University of Keele UK

Since the mid 80's neural computing has been gaining substantial attention as an important computing paradigm. A variety of neural computation models and learning algorithms have been developed and implemented on both general-purpose computers and dedicated hardware. The spectacular advances in VLSI technology over the last few years has further sparked interest and research activities in the field. This paper examines the implementation of neural classification algorithms, the main theme is focused on the parallelisation of a novel neural classifier architecture on three different platforms including the latest on-chip ZISC036 "hyperparallel" neuro-processors. A significant advantage of implementing neural networks directly on silicon is that it overcomes performance limitations of complex networks required for real-time applications. Furthermore, the technology owes much to its efficacy in achieving an algorithmic match between the fine-grained, parallel computation structure of neural architectures and the highly regular VLSI processing model.

关键词： Very large scale integration Neural networks Concurrent computing Artificial neural networks parallel processing Hardware Education Laboratories Computational modeling Silicon

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Hierarchical swapped networks: efficient low-degree alternatives to hypercubes and generalized hypercubes

Hierarchical swapped networks: efficient low-degree alternat...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Chi-Hsiang Yeh B. Parhami Department of Electrical and Computer Engineering University of California Santa Barbara CA USA

In this paper, we propose a new class of interconnection networks called hierarchical swapped networks (HSNs). We show that some subclasses of HSNs can efficiently emulate hypercubes, or generalized hypercubes, while having node degrees significantly smaller than the emulated networks. In particular, a suitably constructed HSN can emulate a hypercube or generalized hypercube with constant slowdown under the single-dimension communication model and asymptotically optimal slowdown with respect to its node degree under the all-port communication model. As a consequence, we obtain a variety of efficient algorithms on HSNs through emulation, thus proving the versatility of HSN. Some subclasses of HSNs are also shown to have asymptotically optimal diameters with respect to their node degrees. HSNs appear to be attractive low-degree alternatives to hypercubes and generalized hypercubes for general-purpose parallel computers.

关键词： Hypercubes Emulation Multiprocessor interconnection networks Concurrent computing parallel architectures Routing Costs

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Computing dominators and its applications on processor arrays with reconfigurable bus systems

Computing dominators and its applications on processor array...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Tzong-Wann Kao Shi-Jinn Horng Department of Electronic Engineering Kuang Wu Institute of Technology and Commerce Taipei Taiwan Department of Electrical Engineering National Taiwan Institute of Technology Taipei Taiwan

ISBN: (纸本)0818674601

Presents an efficient improvement of processor complexity while solving some connectivity problems in processor arrays with reconfigurable bus systems. We first derive two constant time algorithms in the proposed parallel processing system for computing the dominators and the dominator tree of an undirected graph either using a 9-D n/spl times/n/spl times/n processors or a 2-D n/sup 2//spl times/n/sup 2/ processors, where n is the number of vertices of the graph. Then based on the dominator tree algorithm, we also solve many other graph connectivity problems in constant time. They are the articulation points, bridges, biconnected components, and bridge-connected components problems in undirected graphs.

关键词： Tree graphs Bridges Computational modeling parallel algorithms Phase change random access memory Business parallel processing Concurrent computing Processor scheduling Computer networks

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Visualizing high-level communication and synchronization

Visualizing high-level communication and synchronization

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IEEE international Conference on algorithms and architectures for parallel Processing (ICAP)

作者： R. Hofman K. Langendoen H. Bal Department of Mathematics and Computer Science Vrije Universiteit Amsterdam Netherlands

High level parallel languages ease writing of parallel programs. However, since they deepen the gap between language and underlying hardware, performance debugging is herd. It is essential to use tools that present the user with performance data at the language level. Besides this, for hard performance problems it is necessary to be able to descend into the software hierarchy. A trace package and a viewing tool, orcshot, are presented that address these issues for the high level parallel language Orca. Communication and synchronization are done with "shared data objects", and the tool visualizes traces in relation to these objects. Orcshot possesses a powerful filter utility to achieve the necessary data reduction. Orcshot can be adapted to other object based languages with slight effort. The orcshot performance visualization tool has already helped find numerous performance bugs. One example is presented.

关键词： Debugging Hardware Data visualization programming profession parallel languages parallel programming Message passing Runtime Mathematics Computer science

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Analysis, evaluation, and comparison of algorithms for scheduling task graphs on parallel processors

Analysis, evaluation, and comparison of algorithms for sched...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： I. Ahmad Yu-Kwong Kwok Min-You Wu Department of Computer Science Hong Kong University of Science and Technology Hong Kong China Department of Computer Science State University of New York Buffalo NY USA

In this paper, we survey algorithms that allocate a parallel program represented by an edge-weighted directed acyclic graph (DAG), also called a task graph or macro-dataflow graph, to a set of homogeneous processors, with the objective of minimizing the completion time. We analyze 21 such algorithms and classify them into four groups. The first group includes algorithms that schedule the DAG to a bounded number of processors directly. These algorithms are called the bounded number of processors (BNP) scheduling algorithms. The algorithms in the second group schedule the DAG to an unbounded number of clusters and are called the unbounded number of clusters (UNC) scheduling algorithms. The algorithms in the third group schedule the DAG using task duplication and are called the task duplication based (TDB) scheduling algorithms. The algorithms in the fourth group perform allocation and mapping on arbitrary processor network topologies. These algorithms are called the arbitrary processor network (APN) scheduling algorithms. The design philosophies and principles behind these algorithms are discussed, and the performance of all of the algorithms is evaluated and compared against each other on a unified basis by using various scheduling parameters.

关键词： Algorithm design and analysis Scheduling algorithm Processor scheduling Clustering algorithms Computer science Network topology Software algorithms parallel processing Concurrent computing Polynomials

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A parallel reduction algorithm with communication delay

A parallel reduction algorithm with communication delay

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： S. Kurino M. Sakahura Bing Zhang Y. Fukazawa Nihon University Chiyoda Tokyo Japan Waseda University Shinjuku Tokyo Japan

Simulation is an application area for which high speed computation is critical. Massively parallel computers have appeared so that it is now possible to execute very large-scale and complicated simulation without sacrificing accuracy and simplifying problems. For the kind of problems in which the computation in each element depends on the data of all the other elements, a completely-connected network is required in order to simulate with high efficiency. However in massively parallel computers, efficient simulation of these problems is difficult to realize. Its cause is due to their network structure. In this paper, a new network topology which solves these problems with high efficiency and a computation method based on the topology are described.

关键词： Computational modeling Concurrent computing Computer networks Computer simulation Network topology Differential equations Large-scale systems Computer applications Delay effects

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Wormhole routing and its chip design

Wormhole routing and its chip design

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Rong Zeng Xiang Jun Dong Ming Fa Zhu SanCom Company Austin TX USA National Research Center for Intelligent Computing Systems(NC1C) Institute for Computing Technology Beijing China Nat. Res. Center for Intelligent Comput. Acad. Sinica Beijing China

ISBN: (纸本)0818674601

Wormhole routing is a key technique in the design of Dawning 1000 which is the first MPP system made in China. In this paper, wormhole routing is introduced, and an algorithm based on wormhole routing, a chip architecture and its logic design are also described. Finally, an interconnection constructed by the wormhole routing chips is put forward for Dawning 1000 which indicates this kind of chip has a correct function and fast rate with reliability.

关键词： Routing Chip scale packaging Tail Message passing parallel processing Packet switching Delay Intelligent systems Computer architecture Logic design

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Eliminating conditional branches for enhancing instruction level parallelism in VLIW compiler

Eliminating conditional branches for enhancing instruction l...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Seong-Uk Choi Sung-Soon Park Myong-Soon Park Department of Computer Science Korea University Seoul South Korea Department of Computer Science Anyang University South Korea

ISBN: (纸本)0818674601

In VLIW (Very Long Installation Word) compilers, one of the most important issues is how to handle conditional branches, because control dependences are caused by conditional branches and limit the scope of scheduling. This paper proposes the efficient method of eliminating conditional branches. We use SSA (Static Single Assignment) information for preserving semantics. By using our methods, global scheduling techniques can be processed more efficiently and simply. We utilize /spl phi/-functions aggressively, thus computations for code motion are not required. We don't need complex hardware support. Our scheme also makes the performance independent on the result of branch outcomes.

关键词： VLIW Processor scheduling parallel processing Computer science Delay Hardware Performance evaluation

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