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检索条件"任意字段=International Symposium on Parallel Architectures, Algorithms, and Programming"

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Graphical support for data distribution in SPMD parallelization environments

Graphical support for data distribution in SPMD parallelizat...

引用

IEEE international Conference on algorithms and architectures for parallel Processing (ICAP)

作者： R. Koppler S. Grabner J. Volkert Johannes Kepler University Linz Linz Austria Johannes Kepler Universitat Linz Linz AT

The paper introduces a programming environment for HPF like languages with emphasis on graphical support for data distribution. A novel component of this environment is a mapping design and visualization tool. The tool provides visualization of HPF array objects such as data arrays and logical processor arrays and creates a number of diagrams based on information that is gathered from other components of the environment such as the compiler or a debugger. The diagrams relate to crucial issues such as load distribution and communication. Furthermore we show how our environment facilitates seamless integration of additional components.

关键词： Logic arrays Programmable logic arrays programming environments Data visualization Computer architecture Distributed computing Program processors Scientific computing Scalability Costs

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Performance analysis of the doubly-linked list protocol family for distributed shared memory systems

Performance analysis of the doubly-linked list protocol fami...

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IEEE international Conference on algorithms and architectures for parallel Processing (ICAP)

作者： A.C.K. Lau N.H.C. Yung Y.S. Cheung Department of Electrical and Electronic Engineering University of Hong Kong Hong Kong China

The doubly-linked list (DLL) protocol provides a memory efficient, scalable, high-performance and yet easy to implement method to maintain memory coherence in distributed shared memory (DSM) systems. In this paper, the performance analysis of the DLL family of protocols is presented. Theoretically, the DLL protocol with stable owners has the shortest remote memory access latency among the DLL protocol family. According to the simulated performance evaluation, the DLL-S protocol is 65.7% faster than the DDM algorithm for the linear equation solver; and is 16.5% faster for the matrix multiplier. From the trend of the performance figures, it is predicted that the improvement in performance due to the DLL-S protocol will be considerably greater when a larger number of processors are used, indicating that the DLL-S protocol is also the most scalable of the protocols tested.

关键词： Performance analysis Clustering algorithms Access protocols Distributed decision making programming profession Delay Equations Testing parallel processing parallel programming

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Multithreading to improve cycle width and CPI in superpipelined superscalar processors

Multithreading to improve cycle width and CPI in superpipeli...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： B. Goossens Duc Thang Vu IBP-LITP Paris France

This paper presents a multithreaded superpipelined superscalar processor design. It is expected to have a sustained rate of 5.4 instructions run per cycle, with 4 threads on chip. Multithreading serves to improve the superscalar CPI by interleaving threads executions. Operator sharing is used instead of out of order execution. It requires less hardware-no reservation stations, collision vectors or renamed registers-and should offer a greater parallelism potential. Arithmetic operators, including adders, shifters, a multiplier and a step divider, have been pipelined to reduce the processor cycle width to a 16 bits adder propagation delay. Separate and equal lengths data paths controlled by a completely RISC instruction set allow efficient in order issue and termination. Floating point operations are emulated with integer ones with data dependent algorithms providing as good latencies as for traditional hardware implementation. A single register file serves for both the integer and the floating point data.

关键词： Multithreading Pipeline processing Yarn Registers Operating systems Out of order Hardware Propagation delay Arithmetic parallel processing

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Optimal parallel algorithms for computing the chessboard distance transform and the medial axis transform on RAP

Optimal parallel algorithms for computing the chessboard dis...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Yu-Hua Lee Shi-Jinn Horng Tzong-Wann Kao Shung-Shing Lee Department of E.E. National Taiwan Institute of Technology Taiwan Department of E.E. Kuang Wu Institute of Technology and Commerce Taipei Taiwan Department of E.E. Fu-Shin Institute of Technology and Commerce Taiwan

ISBN: (纸本)0818674601

The distance transform (DT) and the medial axis transform (MAT) are two important image operations. They are both used to extract the information about the shape and the position of the foreground pixels relative to each other. Many applications of these transforms are applied in the fields of image processing and computer vision, such as expanding, shrinking, thinning and computing shape factor, etc. Each of these two transforms is essentially a global operation. Unless the digital image is very small, all global operations are prohibitively costly. In order to provide the efficient transform computations, it is considerably desired to develop parallel algorithms for these two operations. In this paper, we provide the fastest parallel algorithms to compute the chessboard distance transform (CDT) which is a DT based on the chessboard metrics, and the medial axis transform (MAT). Each of the transforms of a 2-D binary image array of size N/spl times/N can be computed in O(1) time on the 2-D 2N/spl times/2N reconfigurable array of processors (RAP).

关键词： parallel algorithms Concurrent computing Computer vision Pixel Shape Digital images Image processing Business Data mining Application software

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Finite element analysis with heterogeneous parallel computer environment over ATM network

Finite element analysis with heterogeneous parallel computer...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： H. Fukumori Y. Kono K. Nishimatsu Y. Muraoka School of Science and engineering Waseda University Tokyo Japan Waseda Daigaku Shinjuku-ku Tokyo JP Sch. of Sci. & Eng. Waseda Univ. Tokyo Japan

In this paper, we present an implementation of FEM solver on heterogeneous parallel environment that consists of two different parallel computers (the Fujitsu AP1000 and NEC Cenju-3). We used OLU (On Line University) Network, which is one of the wide area ATM network connecting over 20 universities and research facilities all over Japan. We used substructure method applied in multiple levels for the calculation algorithm. This algorithm, has small data dependency in the calculation phase and the number of data transfer between the parallel computers is limited, thus the overhead for the synchronization can be smaller than iterative method, This paper also refers to the parallel triangular mesh generator based on the Delaunay Triangulation currently being implemented on the Fujitsu AP1000 parallel computer.

关键词： Computer networks Concurrent computing National electric code Joining processes Virtual colonoscopy Network topology Equations Assembly

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High-Performance Fortran and possible extensions to support conjugate gradient algorithms 96

High-Performance Fortran and possible extensions to support ...

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international symposium on High Performance Distributed Computing

作者： K. Dincer G.C. Fox K. Hawick School of Computer and Information Sciences Northeast Parallel Architectures Center Syracuse University NY USA

ISBN: (纸本)9780818675829

Evaluates the High Performance Fortran (HPF) language for the compact expression and efficient implementation of conjugate-gradient iterative matrix-solvers on high-performance computing and communications (HPCC) platforms. We discuss the use of intrinsic functions, data distribution directives and explicitly parallel constructs to optimize performance by minimizing communications requirements in a portable manner. We focus on implementations using the existing HPF definitions but also discuss issues arising that may influence a revised definition for HPF-2. Some of the codes discussed are available on the World Wide Web at http://***/hpfa/, along with other educational and discussion material related to applications in HPF.

关键词： Character generation Sparse matrices Concurrent computing programming profession Equations Iterative algorithms Physics computing Distributed computing Program processors Fluid dynamics

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Computing with heterogeneous parallel machines: advantages and challenges

Computing with heterogeneous parallel machines: advantages a...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： H.J. Siegel Lee Wang V.P. Roychowdhury Min Tan Parallel Processing Laboratory School of Electrical and Computer Engineering Purdue University West Lafayette IN USA

Discusses the advantages of computing with heterogeneous parallel machines, and examines the research challenges for automating the use of such systems. One type of heterogeneous computing system is a mixed-mode machine, where a single machine can operate in different modes of parallelism. Another is a mixed-machine system, where a suite of different kinds of parallel machines are interconnected by high-speed links. To exploit such systems, a task must be decomposed into subtasks, where each subtask is computationally homogeneous. The subtasks are then assigned to and executed with the machines (or modes) that will result in a minimal overall execution time. Typically, users must specify this decomposition and assignment. One long-term pursuit in heterogeneous computing is to do this automatically. An overview of a conceptual model of what this involves is given. As an example of the research in this area, a genetic-algorithm-based approach to the subtask assignment and scheduling problem is explored. Open problems in heterogeneous computing are described.

关键词： Concurrent computing parallel machines parallel processing Laboratories Switches Processor scheduling Supercomputers Computer architecture Contracts Subcontracting

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parallel tertiary structure search on the Cenju-S parallel machine

Parallel tertiary structure search on the Cenju-S parallel m...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： M. Asogawa C&C Systems Research Laboratories NEC Corporation Limited Kawasaki Kanagawa Japan

The author parallelized a tertiary structure search algorithm on a distributed memory parallel computer, Cenju-S, utilizing a standard message passing interface (MPI) parallel library. For parallelization scheme, a master-workers model is used. The author analyzed the total performance by utilizing a M/M/1 queueing model and Jackson's model, and clearly explained the actual turn around times. Tertiary structure search is a computationally intensive task. When test sequences are distributed to all processors, a single key sequence can be tested independently. Thus high parallelization results are anticipated. Since database is allocated on a master processor, worker processors should acquire test sequences from the master processor. Sometimes a worker should wait until other workers obtain test sequences from the master processor. By this waiting, the total performance will saturate when the number of processors proceeds certain level.

关键词： parallel machines Testing Computer interfaces Concurrent computing Distributed computing Message passing Libraries Performance analysis Queueing analysis Databases

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Architecture of a fast motion estimator for MPEG video coding

Architecture of a fast motion estimator for MPEG video codin...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Nam Ling R. Advani Computer Engineering Department Santa Clara University Santa Clara CA USA

This paper describes the design of a high speed motion estimator using the 2-D log search algorithm. The architecture consists of 5 simple processing elements (PE) where each PE is capable of computing the sum-of-absolute-difference (SAD) to exploit the parallelism. For each step in the 2-D log search procedure, the 5 SADs of the 5 search points are computed in parallel. The design is implemented using Verilog and synthesized using Synopsys. Such a chip would be able to generate the motion vector for each 16*16 macroblock in 14.58 /spl mu/s for 3-step log search, and 24.30 /spl mu/s for 5-step log search. The architecture is well suited for encoding MPEG2 video up to MP@ML.

关键词： Motion estimation Video coding Computer architecture Video compression Concurrent computing Electronic mail parallel processing Hardware design languages Encoding Broadband communication

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DDB: a distributed debugger based on replay

DDB: a distributed debugger based on replay

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IEEE international Conference on algorithms and architectures for parallel Processing (ICAP)

作者： J. Sienkiewicz T. Radhakrishnan Software Engineer Ericsson Research Canada Mont Royal QUE Canada Department of Computer Science Concordia University Montreal Canada

DDB is a distributed debugger that is based on the well known technique of "Instant Replay". The debugger is designed and implemented to operate under multithreaded Mach Distributed Operating System. It is complete in the sense that a graphical user interface, source code level debugging facility at the individual nodes of the distributed computation, and our experience in using the debugger are well documented. We provide, in this paper, a brief, but complete view of DDB from which the developers of new debuggers for parallel and distributed systems can benefit.

关键词： Debugging Probes Computer bugs Yarn Synchronization programming profession Computer errors Clocks Delay Timing

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