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检索条件"任意字段=International Symposium on Parallel Architectures, Algorithms, and Programming"

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Swing module scheduling: a lifetime-sensitive approach

Swing module scheduling: a lifetime-sensitive approach

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international Conference on parallel Architecture and Compilation Techniques (PACT)

作者： J. Llosa A. Gonzalez E. Ayguade M. Valero Departament d Arquitectura de Computadors Universitat Poliltècnica de Catalunya Barcelona Spain

This paper presents a novel software pipelining approach, which is called Swing Modulo Scheduling (SMS). It generates schedules that are near optimal in terms of initiation interval, register requirements and stage count. Swing Modulo Scheduling is an heuristic approach that has a low computational cost. The paper describes the technique and evaluates it for the Perfect Club benchmark suite. SMS is compared with other heuristic methods showing that it outperforms them in terms of the quality of the obtained schedules and compilation time. SMS is also compared with an integer linear programming approach that generates optimum schedules but with a huge computational cost, which makes it feasible only for very small loops. For a set of small loops, SMS obtained the optimum initiation interval in all the cases and its schedules required only 5% more registers and a 1% higher stage count than the optimum.

关键词： Processor scheduling Pipeline processing Registers Proposals Throughput Scheduling algorithm Computational efficiency Integer linear programming parallel processing Iterative algorithms

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parallel implementation of Bouvka's minimum spanning tree algorithm

Parallel implementation of Bouvka's minimum spanning tree al...

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international symposium on parallel Processing

作者： Sun Chung A. Condon Computer Sciences Department University of Wisconsin Madison WI USA

We study parallel algorithms for the minimum spanning tree problem, based on the sequential algorithm of O. Boruvka (1926). The target architectures for our algorithm are asynchronous, distributed-memory machines. Analysis of our parallel algorithm on a simple model that is reminiscent of the LogP model, shows that in principle a speedup proportional to the number of processors can be achieved, but that communication costs can be significant. To reduce these costs, we develop a new randomized linear work pointer jumping scheme that performs better than previous linear work algorithms. We also consider empirically the effects of data imbalance on the running time. For the graphs used in our experiments, load balancing schemes result in little improvement in running times. Our implementations on sparse graphs with 64,000 vertices on Thinking Machine's CM-5 achieve a speedup factor of about 4 on 16 processors. On this environment, packaging of messages turns out to be the most effective way to reduce communication costs.

关键词： Costs parallel algorithms Algorithm design and analysis Load management Packaging machines

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Practical parallel algorithms for dynamic data redistribution, median finding, and selection

Practical parallel algorithms for dynamic data redistributio...

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international symposium on parallel Processing

作者： D.A. Bader J. JaJa Institute for Advanced Computer Studies and Department of Electrical Engineering University of Maryland College Park MD USA

A common statistical problem is that of finding the median element in a set of data. This paper presents a fast and portable parallel algorithm for finding the median given a set of elements distributed across a parallel machine. In fact, our algorithm solves the general selection problem that requires the determination of the element of rank i, for an arbitrarily given integer i. Practical algorithms needed by our selection algorithm for the dynamic redistribution of data are also discussed. Our general framework is a distributed memory programming model enhanced by a set of communication primitives. We use efficient techniques for distributing, coalescing, and load balancing data as well as efficient combinations of task and data parallelism. The algorithms have been coded in SPLIT-C and run on a variety of platforms, including the Thinking Machines CM-5, IBM SP-1 and SP-2, Gray Research T3D, Meiko Scientific CS-2, Intel Paragon, and workstation clusters. Our experimental results illustrate the scalability and efficiency of our algorithms across different platforms and improve upon all the related experimental results known to the authors.

关键词： parallel algorithms Clustering algorithms parallel machines Heuristic algorithms Load management Workstations Scalability

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parallel intersecting compressed bit vectors in a high speed query server for processing postal addresses

Parallel intersecting compressed bit vectors in a high speed...

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IEEE symposium on High-Performance Computer Architecture

作者： Wen-Jann Yang R. Sridhar V. Demjanenko Department of Electrical and Computer Engineering State University of New York University at Buffalo Buffalo NY USA

A parallel architecture is proposed for a high speed query server to process postal addresses with several fields. For a given component in a field, the offset addresses of records which contain the component in a postal address database are coded into a Compressed Bit Vector (CBV). Finding the appropriate CBVs and performing intersections to get matching offset addresses are key bottleneck for the performance in the query server. They are accomplished by a specialized hardware embedded in a general purpose computer for a cost effective solution. This hardware directly operates on the CBVs using parallel schemes. The architecture and algorithms for expanding a CBV, for synchronizing the parallel processing of the processing units, and for balancing the load in the pipelined stages are presented with simulation results.

关键词： Databases Hardware Costs parallel processing Embedded computing Computer architecture parallel architectures Computational modeling High performance computing System performance

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Proceedings of SPDP '96: 8th IEEE symposium on parallel and Distributed Processing

Proceedings of SPDP '96: 8th IEEE Symposium on Parallel and ...

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international Conference on Engineering and Technology Management (IEMC)

作者： Qingrui Xu Bin Guo Jin Chen Research Center of Management Science and Strategy Development School of Management University of Zhejiang Hangzhou China

Presents the title page of the proceedings record.

ISBN: (纸本)078033552X

Presents the title page of the proceedings record.

关键词： parallel processing distributed processing multiprocessor interconnection networks graph theory networks routing distributed systems scheduling data mapping parallel architectures graph theory wormhole routing sorting synchronisation I/O load balancing parallel algorithms languages compilers interconnection networks embedding

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Heterogeneous parallel architecture for improving signal processing performance in Doppler blood flow instrumentation

Heterogeneous parallel architecture for improving signal pro...

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Workshop on parallel and Distributed Real-Time Systems

作者： D.F. Garcia Nocetti J. Solano Gonzalez J. Martinet Flores D. Ramos Hernandez IIMAS UNAM DEA Mexico Mexico

The work presents a heterogeneous parallel approach, for implementing a model based spectral estimation method, based on the modified covariance parametric algorithm. A Heterogeneous Processing Node (HPN) has been developed, which combines the communications ability of the transputer with a high performance signal processing of a DSP, in order to improve the time performance in parametric spectral estimation. The HPN includes libraries for downloading and executing precompiled ready to run DSP functions, using standard transputer programming tools. The heterogeneous approach has been used in a case study concerning parametric spectral estimation of Doppler ultrasound signals. Performance analysis and results are presented with respect to a homogeneous approach, revealing the effectiveness of the heterogeneous approach.

关键词： parallel architectures Signal processing Digital signal processing Computer architecture Signal processing algorithms Concurrent computing Blood flow Instruments Libraries Functional programming

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Efficient algorithms for block-cyclic redistribution of arrays

Efficient algorithms for block-cyclic redistribution of arra...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Young Won Lim P.B. Bhat V.K. Prasanna Department of EE-Systems University of Southern California Los Angeles CA USA

We present new algorithmic techniques for a classical research problem, runtime redistribution of an array from one block-cyclic layout to another. Our methodology for reducing communication overheads is based on a generalized circulant matrix formalism. Using this formalism, we derive direct, indirect, and hybrid communication schedules for the cyclic redistribution problem when the block size changes by an integer factor K. We have also developed formulae to estimate the timing performance of each of these schedules for a given parallel machine and redistribution problem. In our indirect communication schedule, blocks are moved from a source processor to a destination processor through intermediate "relay" processors. This reduces the number of communication steps by an order of magnitude, in comparison with previous approaches. This algorithm performs cyclic(x) to cyclic(Kx) redistribution on P processors in [log/sub 2/K]+2 steps. Implementations of these algorithms on the Cray T3D and on the IBM SP-2 show superior performance over previous approaches. Since our algorithms are developed using MPI, they can be easily ported to different application environments. Our techniques can be used in the design of scalable redistribution libraries, in efficient implementations of the REDISTRIBUTE directive of HPF and in developing parallel algorithms for various HPC applications.

关键词： Signal processing algorithms Processor scheduling parallel machines Algorithm design and analysis Libraries parallel algorithms High performance computing Program processors programming profession Search problems

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Using memory-mapped network interfaces to improve the performance of distributed shared memory

Using memory-mapped network interfaces to improve the perfor...

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IEEE symposium on High-Performance Computer Architecture

作者： L.I. Kontothanassis M.L. Scott Department of Computer Science University of Rochester Rochester NY USA

Shared memory is widely believed to provide an easier programming model than message passing for expressing parallel algorithms. Distributed Shared Memory (DSM) systems provide the illusion of shared memory on top of standard message passing hardware at very low implementation cost, but provide acceptable performance for only a limited class of applications. We argue that the principal sources of overhead overhead in DSM systems can be dramatically reduced with modest amounts of hardware support (substantially less than is required for hardware cache coherence). Specifically, we present and evaluate a family of protocols designed to exploit hardware support for a global, but non-coherent, physical address space. We consider systems both with and without remote cache fills, fine-grain access faults, "doubled" writes to local and remote memory, and merging write buffers. We also consider varying levels of latency and bandwidth. We evaluate our protocols using execution driven simulation, comparing them to each other and to a state-of-the-art protocol for traditional message-based networks. For the programs in our application suite, protocols taking advantage of the global address space improve performance by a minimum of 50% and sometimes by as much as an order of magnitude.

关键词： Network interfaces Hardware Access protocols Message passing parallel programming parallel algorithms Costs Coherence Merging Delay

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Sorting N items using a p-sorter in optimal time

Sorting N items using a p-sorter in optimal time

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international symposium on parallel and Distributed Processing (IPDPS)

作者： S. Olarin S.Q. Zheng Dept. of Comput. Sci. Old Dominion Univ. Norfolk VA USA Department of Computer Science Louisiana State University Baton Rouge LA USA

A sorting device capable of sorting p items in constant time is called a p-sorter. It is known that the task of sorting N items using a p-sorter requires at least /spl Omega/ (N log N/p log p) applications of the p-sorter. This bound is tight: there exist algorithms that use O (N log N/p log p) calls to the p-sorter to sort N items. However, there is no known implementable algorithm that can sort N items in O(N log N/p log p) time using a p-sorter. The main contribution of this paper is to propose a simple VLSI architecture and to show that in our architecture N items can be sorted in O(N log N/p log p) calls to the p-sorter, while enforcing conflict-free memory accesses. An important feature of our design is that the total additional VLSI area for hardware, other than the memory for data and the p-sorter, is kept to a minimum.

关键词： Sorting Very large scale integration Computer architecture Computer science Semiconductor device measurement Application software Hardware parallel algorithms parallel processing parallel architectures

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Portable transparent checkpointing for distributed shared memory 96

Portable transparent checkpointing for distributed shared me...

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international symposium on High Performance Distributed Computing

作者： L.M. Silva J.G. Silva S. Chapple Departamento Engenharia Informática Universidade de Coimbra Polo II Coimbra Portugal Edinburgh Parallel Computing Centre University of Edinburgh Edinburgh UK

ISBN: (纸本)9780818675829

We present a checkpointing mechanism for a DSM system that, in spite of being invisible to the programmer, is quite efficient and portable. It is efficient because it is nonblocking, coordinated and thus domino-effect free. It offers some portability because it is built on top of MPI and uses only the services offered by MPI and a POSIX compliant local file system. As far as we know, this is the first real implementation of such a scheme for DSM. Along with the description of the algorithms used, we present experimental results obtained in a cluster of workstations, and discuss many insights that came out of the implementation effort. We hope that our research shows that efficient, transparent and portable checkpointing is viable for DSM systems.

关键词： Checkpointing Workstations parallel machines Fault tolerant systems programming profession File systems Clustering algorithms Scalability Computer crashes Distributed computing

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