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A study of the communication cost of the FFT on torus multicomputers

A study of the communication cost of the FFT on torus multic...

引用

IEEE international Conference on algorithms and architectures for parallel Processing (ICAP)

作者： L.D. de Cerio M. Valero-Garcia A. Gonzalez Departament d' Arqitectma de Computadors University Politiknica de Catalunya Barcelona Spain Universitat Politecnica de Catalunya Barcelona Catalunya ES Dept. d'Arquitectura de Computadors Univ. Politecnica de Catalunya Barcelona Spain

The computation of a one-dimensional FFT on a c-dimensional torus multicomputer is analyzed. Different approaches are proposed which differ in the way they use the interconnection network. The first approach is based on the multidimensional index mapping technique for the FFT computation. The second approach starts from a hypercube algorithm and then embeds the hypercube onto the torus. The third approach reduces the communication cost of the hypercube algorithm by pipelining the communication operations. A novel methodology to pipeline the communication operations on a torus is proposed. Analytical models are presented to compare the different approaches. This comparison study shows that the best approach depends on the number of dimensions of the torus and the communication start-up and transfer times. The analytical models allow us to select the most efficient approach for the available machine.< >

关键词： Costs Message passing Memory management Multidimensional systems programming profession Hypercubes Pipeline processing Distributed computing Analytical models Computer networks

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A method of optimising data distribution on a loosely coupled multiprocessor system

A method of optimising data distribution on a loosely couple...

引用

IEEE international Conference on algorithms and architectures for parallel Processing (ICAP)

作者： A. Symons V.L. Narasimhan Department of Electrical and Computer Engineering The PASE Researach Laboratory University of Queensland QLD Australia

The maximum speedup of a multiprocessor system is limited by the sequential part of an algorithm and in loosely coupled processor systems, a large part of this sequentiality is caused by the communication between processors. As this communication is dependent on the distribution of data the data distribution must be optimised in order to achieve the maximum speedup. In this paper we present a new method of achieving this optimisation for loosely coupled multiprocessors using a branch and bound technique based on the Moore-Skelboe interval arithmetic. Two key issues of this algorithm have been addressed, namely, the branch selection criterion, and an efficient data structure to keep track of the branches. A blocked data structure is shown to have the desirable properties of dynamic list length, and minimal disk thrashing. When this method is applied to an FFT algorithm running on a pipeline of transputers, the optimised data distribution is shown to yield an improved speedup over the equal and random distributions, which do not take into account communication overheads.< >

关键词： Optimization methods Multiprocessing systems Mathematical model Robustness Arithmetic Data structures Processor scheduling Load management Linear programming Network topology

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Loop scheduling for heterogeneity 95

Loop scheduling for heterogeneity

引用

international symposium on High Performance Distributed Computing

作者： M. Cierniak Wei Li M.J. Zaki Computer Science Department University of Rochester Rochester NY USA

ISBN: (纸本)9780818670886

In this paper we study the problem of scheduling parallel loops at compile-time for a heterogeneous network of machines. We consider heterogeneity in three aspects of parallel programming: program, processor and network. A heterogeneous program has parallel loops with different amount of work in each iteration; heterogeneous processors have different speeds; and a heterogeneous network has different cost of communication between processors. We propose a simple yet comprehensive model for use in compiling for a network of processors, and develop compiler algorithms for generating optimal and sub-optimal schedules of loops for load balancing, communication optimizations and network contention. Experiments show that a significant improvement of performance is achieved using our techniques.

关键词： Processor scheduling Scheduling algorithm Load management parallel machines parallel programming Asynchronous transfer mode Workstations Dynamic programming Computer science Costs

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An analytical comparison of nearest neighbor algorithms for load balancing in parallel computers

An analytical comparison of nearest neighbor algorithms for ...

引用

international symposium on parallel Processing

作者： Chengzhong Xu B. Monien R. Luling F.C.M. Lau Department of Electrical and Computer Engineering Wayne State University MI USA Department of Computer Science University of Paderborn Germany Department of Computer Science University of Hong Kong Hong Kong China

With nearest neighbor load balancing algorithms, a processor makes balancing decisions based on its local information and manages work load migrations within its neighborhood. This paper compares a couple of fairly well-known nearest neighbor algorithms, the dimension exchange and the diffusion methods and their variants in terms of their performances in both one-port and all-port communication architectures. It turns out that the dimension exchange method outperforms the diffusion method in the one-port communication model, and that the strength of the diffusion method is in asynchronous implementations in the all-port communication model. The underlying communication networks considered assume the most popular topologies, the mesh and the torus and their special cases: the hypercube and the k-ary n-cube.< >

关键词： Algorithm design and analysis Nearest neighbor searches Load management Concurrent computing Computer networks Approximation algorithms Bandwidth

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Learning in neuro/fuzzy analog chips

Learning in neuro/fuzzy analog chips

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： A. Rodriguez-Vazquez F. Vidal-Verdu Department de Arquitectura y Tecnología de Computadores y Electróica Universidad de Málaga Molaga Spain Department of Analog Design CNM Seville Spain

This paper focus on the design of adaptive mixed-signal fuzzy chips. These chips have parallel architecture and feature electrically-controllable surface maps. The design methodology is based on the use of composite transistors-modular and well suited for design automation. This methodology is supported by dedicated, hardware-compatible learning algorithms that combine weight-perturbation and outstar.

关键词： Circuits Fuzzy systems Design methodology Inference algorithms Very large scale integration CMOS technology Analog computers parallel architectures Design automation Fuzzy control

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Optimal architecture-independent scheduling of fine-grain tree-sweep computations

Optimal architecture-independent scheduling of fine-grain tr...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Lixin Gao A.L. Rosenberg R.K. Sitaraman Department of Computer Science University of Massachusetts Amherst MA USA

We present algorithms for optimally scheduling computations that comprise a sequence of complete up- and/or down-sweeps on a complete binary tree, on a parallel architecture in which the communication delay between any two processors is uniform. Such computations include, for instance, those that implement broadcast, accumulation, and the parallel-prefix operator; such architectures include, for instance, networks of workstations. Our schedules are optimal in the sense of having the actual minimum time-to-completion-not just on approximation thereof-considering the time for both computation and communication. We concentrate on schedules for fine-grain tree-sweep computations-wherein communication costs are rather large relative to per-task computation cost.

关键词： Processor scheduling Concurrent computing Computational efficiency Scheduling algorithm Binary trees parallel architectures Delay Computer networks Broadcasting Computer architecture

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Transformable computers & hardware object technology

Transformable computers & hardware object technology

引用

international symposium on parallel Processing

作者： J. Schewel M. Thornburg S. Casselman Virtual Computer Corporation Reseda CA USA

We define transformable computing systems as those machines that use the reconfigurable aspects of field programmable gate arrays (FPGA) to implement an algorithm. Researchers throughout the world have shown that computationally intensive software algorithms can be transposed directly into hardware design for extreme performance gain. The on-the-fly use of digital designs in a reconfigurable computer can easily be utilized from within existing software applications. Hardware objects are converted digital designs called from within a software program. This H.O.T. (Hardware Object Technology) method of programming transformable computers is the subject of this paper.< >

关键词： Hardware Field programmable gate arrays Application software Algorithm design and analysis Software performance Computer interfaces Computational modeling Computer simulation programming environments Random access memory

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Highly parallel VLSI architectures for linear convolution

Highly parallel VLSI architectures for linear convolution

引用

IEEE international symposium on Circuits and Systems (ISCAS)

作者： A. Elnaggar H.M. Alnuweiri M.R. Ito Department of Electrical Engineering University of British Columbia Vancouver BC Canada

This paper presents highly parallel VLSI structures for linear convolution. Our methodology implements Toom's algorithm and is based on mapping a modified version of the tensor product factorization proposed by Granata et al. (1991). The resulting networks have very simple structure, highly regular topology, and use simple bit-serial devices. Additionally, the proposed networks have very small depth and contain only a single stage of multipliers, while all other stages contain adders only.

关键词： Very large scale integration Convolution Matrix decomposition Tensile stress Signal processing algorithms parallel processing Matrix converters Network topology Digital signal processing Multidimensional systems

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Experience with active messages on the Meiko CS-2

Experience with active messages on the Meiko CS-2

引用

international symposium on parallel Processing

作者： K.E. Schauser C.J. Scheiman Department of Computer Science University of California슠Santa Barbara Santa Barbara CA USA

Active messages provide a low latency communication architecture which on modern parallel machines achieves more than an order of magnitude performance improvement over more traditional communication libraries. This paper discusses the experience we gained while implementing active messages on the Meiko CS-2, and discusses implementations for similar architectures. During our work we have identified that architectures which only support efficient remote write operations (or DMA transfers as in the case of the CS-2) make it difficult to transfer both data and control as required by active messages. Traditional network interfaces avoid this problem because they have a single point of entry which essentially acts as a queue. To efficiently support active messages on modern network communication co-processors, hardware primitives are required which support this queue behavior The overcame this problem by producing specialized code which runs on the communications co-processor and supports the active messages protocol. Our implementation of active messages results in a one-way latency of 12.3 /spl mu/s and achieves up to 39 MB/s for bulk transfers. Both numbers are close to optimal for the current Meiko hardware and are competitive with performance of active messages on other hardware platforms.< >

关键词： Hardware Delay Coprocessors Libraries Space exploration Workstations Computer science parallel machines Protocols programming profession

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Global predicates in rough real time

Global predicates in rough real time

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international symposium on parallel and Distributed Processing (IPDPS)

作者： J. Mayo P. Kearns Department of Computer Science Williamsburg VA USA

Evaluation of predicates on the state of a distributed system is complicated by the lack of either a common clock or common memory. In these systems, message passing is often used to order local events globally. This leads to a partial, causal ordering of system events. Predicate evaluation algorithms based on this causal ordering generally cannot determine if an unstable predicate was true at some instant of real time without freezing the underlying application. They only determine whether or not the predicate could have occurred. This ordering is sufficient for evaluating stable predicates, but algorithms based on it require a good deal of message passing. We present two algorithms which conclusively evaluate both stable and a restricted class of unstable predicates for a given execution. The algorithms are based on the use of roughly synchronized clocks. We present an algorithm for scheduled evaluation as well as a centralized detection algorithm.

关键词： Clocks Message passing Synchronization Computer science Detection algorithms programming Counting circuits

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