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检索条件"任意字段=International Symposium on Parallel Architectures, Algorithms, and Programming"

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Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations

Overview of the JUMP-1, an MPP prototype for general-purpose...

引用

international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： K. Hiraki H. Amano M. Kuga T. Sueyoshi T. Kudoh H. Nakashima H. Nakajo H. Matsuda T. Matsumoto S. Mori University of Tokyo Japan Keio University Japan Kyushu Institute of Technology Japan Tokyo Engineering University Japan Kyoto University Japan Kobe University Japan

We describe the basic architecture of JUMP-1, an MPP prototype developed by collaboration between 7 universities. The proposed architecture can exploit high performance of coarse-grained RISC processor performance in connection with flexible fine-grained operation such as distributed shared memory, versatile synchronization and message communications.< >

关键词： Prototypes Concurrent computing Protocols Memory architecture Yarn Switches parallel processing Distributed computing Power system protection Communication switching

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On a sublinear time parallel construction of optimal binary search trees 19th

On a sublinear time parallel construction of optimal binary ...

引用

19th international symposium on Mathematical Foundations of Computer Science, MFCS 1994

作者： Karpinski, Marek Rytter, Wojciech Department of Computer Science University of Bonn Bonn53117 Germany The International Computer Science Institute Berkeley United States Department of Computer Science University of Warsaw Warsaw02-097 Poland

ISBN: (纸本)9783540583387

We design an efficient sublinear time parallel construction of optimal binary search trees. The efficiency of the parallel algorithm corresponds to its total work (the product time × processors). Our algorithm works in O(n1−ɛlog n) time with the total work O(n2+2ɛ), for an arbitrarily small constant 0 2ɛwith respect to the best known sequential algorithm given by Knuth, which needs only O(n2) time due to a monotonicity property of optimal binary search trees, see [6]). It is unknown how to explore this property in an efficient NC construction of binary search trees. Here we show that it can be effectively used in sublinear time parallel computation. Our improvement also relies on the use (in independently processed small subcomputations) of the parallelism present in Knuth’s algorithm. The best known sublinear time algorithms for the construction of binary search trees (as an instance of a more general problem) have O(n3) work for time larger than n3/4, see [3] and [7]. For time √n these algorithms need n4 work, while our algorithm needs for this time only n3work, thus improving the known algorithms by a linear factor. Also if time is O(n1−ɛ) and Ε is very small our improvement is close to O(n). Such improvement is similar to the one implied by the monotonicity property in sequential computations (from n3sequential time for a more general dynamic programming problem to n2time for the special case of optimal binary search trees). © 1994, Springer Verlag. All rights reserved.

关键词： Dynamic programming

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Software pipelining for Jetpipeline architecture

Software pipelining for Jetpipeline architecture

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： M. Katahira T. Sasaki Hong Shen H. Kobayashi T. Nakamura Graduate School of Information Sciences University of Tohoku Sendai Japan

High performance processors based on pipeline processing play an important role in scientific computation. We have proposed a hybrid pipeline architecture named Jetpipeline in our former work. The concept of Jetpipeline comes from the integration of superscalar, VLIW and vector architectures. Jetpipeline has multiple instruction pipelines, which execute multiple instructions like superscalar architectures. Instructions to be executed simultaneously are statically scheduled by a compiler like VLIW architectures. Therefore, parallelism derivation and instruction scheduling are very important for Jetpipeline. Software pipelining is one of the well-known techniques to achieve high throughput when processing loop programs. In this paper, we propose software pipelining for Jetpipeline. Firstly, the overview of the Jetpipeline architecture is described. Then the banked register configuration of Jetpipeline for reducing hardware complexity and supporting software pipelining is presented. Finally, the effectiveness of software pipelining for Jetpipeline is discussed by simulation.< >

关键词： Pipeline processing Computer architecture VLIW Hardware parallel processing High performance computing Processor scheduling Throughput Registers Computational modeling

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Views of mixed-mode computing and network evaluation

Views of mixed-mode computing and network evaluation

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： H.-J. Siegel J.K. Antonio School of Electrical Engineering Parallel Processing Laboratory Purdue University West Lafayette IN USA

Trade-offs between the SIMD and MIMD models of architecture for parallelism are presented. Mixed-mode parallelism, where a machine can switch between the SIMD and MIMD modes of parallelism at instruction-level granularity with generally negligible overhead, is discussed. Advantages and disadvantages of mixed-mode parallelism and an example of a mixed-mode parallel algorithm are given. The relationship of mixed-mode processing to high-performance heterogeneous computing is overviewed. Difficulties involved with evaluating interconnection networks for parallel machines are then considered. There are a myriad of metrics that have been used in the literature. The problems involved with choosing the most appropriate metric or weighted set of metrics, and performing "fair" comparisons, are explored.< >

关键词： Computer networks parallel processing Concurrent computing Switches Multiprocessor interconnection networks Computer aided instruction Broadcasting Laboratories Computer architecture parallel machines

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Efficient algorithms for conservative parallel simulation of interconnection networks

Efficient algorithms for conservative parallel simulation of...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Yong Meng Teo Seng Chuan Tay Department of Information Systems & Computer Science National University of Singapore Singapore Singapore

ISBN: (纸本)0818665076

This paper addresses the use of parallel simulation techniques to speedup the simulation of multistage interconnection networks. The conventional null-message approach to resolving deadlock problem in conservative simulation is based on a lookahead mechanism. For some application domains, unfortunately, the lookahead information is not available. Consequently, the simulation using null messages will be trapped in a livelock. We propose a deadlock/livelock free scheme using null messages, but without the guaranteed lookahead, to coordinate the simulation, and different partitioning techniques for mapping of the simulation program onto multicomputers. A flushing mechanism to address the combinatoric explosion of using null-message in conservative simulation is also discussed. Our analysis shows that the proposed flushing mechanism effectively reduces the number of null messages from exponential to linear.< >

关键词： Multiprocessor interconnection networks Computational modeling Switches Computer simulation System recovery Performance analysis Traffic control Multiprocessing systems Delay Analytical models

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All-to-all communication on meshes with wormhole routing

All-to-all communication on meshes with wormhole routing

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international symposium on parallel Processing

作者： R. Thakur A. Choudhary Northeast Parallel Architectures Center Syracuse University Syracuse NY USA

Describes several algorithms to perform all-to-all communication on a two-dimensional mesh connected computer with wormhole routing. The authors discuss both direct algorithms, in which data is sent directly from source to destination processor, and indirect algorithms in which data is sent through one or more intermediate processors. The authors propose algorithms for both power-of-two and non power-of-two meshes as well as an algorithm which works for any arbitrary mesh. They have developed analytical models to estimate the performance of the algorithms on the basis of system parameters. Performance results obtained on the Intel Touchstone Delta are compared with the estimated values.< >

关键词： Routing Concurrent computing Analytical models Delay parallel architectures Educational institutions Computer networks Distributed computing Etching Application software

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Processing nested loop structure with data-flow dependence on a CAM-based processor HAPP

Processing nested loop structure with data-flow dependence o...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Kuei-Ming Lu K. Tamaru Department of Electronic Engineering Kyoto University Japan

We know that a significant advantage of content addressable memory (CAM) is that operations are performed locally, thus it can eliminate the problem of bottleneck between processor and memory. In this paper, we propose a CAM-based associative processing processor (HAPP) which is able to combine with a general processor to form an array-processor system, and besides retrieval operations, it can assist the general processor to manipulate nested loop structure with data-flow dependence for achieving high speedup in this system. We enumerate some problems of applying HAPP to a computer system to deal with nested loop structure, and the methods we used to resolve them. Also we compare HAPP with a parallel machine, BBN TC2000, to prove that HAPP gains a smaller communication penalty when the number of data items access of BBN TC2000 surpasses penalty plane.< >

关键词： Computer aided manufacturing CADCAM Information retrieval Associative memory Data mining parallel processing Concurrent computing Associative processing Integrated circuit technology parallel architectures

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Investigating weak memories using Maya

Investigating weak memories using Maya

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international symposium on High Performance Distributed Computing

作者： D. Agrawal M. Choy Hong Va Leong A.K. Singh Department of Computer Science University of California슠Santa Barbara Santa Barbara CA USA

Maya is a platform for investigating the impact of different memory coherence protocols on parallel architectures. We present the implementations of several weak memory protocols, together with some new primitives dedicated to weak memories using Maya. The results of some user applications are summarized and the impact of weak memories on the efficiency of these parallel programs is discussed.< >

关键词： Delay Random access memory Access protocols Computer science parallel architectures parallel programming Hardware programming profession Costs Laboratories

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parallel connectivity algorithms on permutation graphs

Parallel connectivity algorithms on permutation graphs

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Yi-Wen Chen Shi-Jinn Horng Tzong-Wann Kao Horng-Ren Tsai Shun-Shan Tsai Department of Electrical Engineering National Taiwan Institute of Technology Taipei Taiwan

ISBN: (纸本)0818665076

In this paper, we shall present several algorithms for determining the maximum number of vertex connectivity, testing k-vertex connectivity, determining the maximum number of vertex disjoint s-t paths and finding k-vertex disjoint s-t paths problems on a permutation graph, respectively. We first give several O(n/sup 2/) time sequential algorithms for determining the maximum number of vertez connectivity, testing k-vertex connectivity and determining the maximum number of vertex disjoint s-t paths problems, respectively. Then, an O(kn/sup 2/) time algorithm for finding k-vertex disjoint s-t paths problem on a permutation graph is also proposed. Moreover, we also derive the corresponding parallel algorithms for these problems from the proposed sequential algorithms. On the EREW PRAM model, we first propose several O(log n) time optimal speed-tip parallel algorithms for determining the maximum m number of vertez connectivity, testing k-vertex connectivity and determining the maximum number of vertex disjoint s-t paths problems, all with O(n/sup 2/log n) processors, respectively. Then, an O(nlog n) time parallel algorithm for finding k-vertex disjoint s-t paths problem using O(n/sup 2/log n) processors is also developed, where k is a fixed integer.< >

关键词： parallel algorithms Testing Sequential analysis Phase change random access memory Graph theory Circuit synthesis Reliability theory parallel architectures Terminology Artificial intelligence

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HyperC: portable parallel programming in C

HyperC: portable parallel programming in C

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international symposium on parallel Processing

作者： P. Clermont N. Paris Projet X-Pôle-Ecole Polytechnique HyperParallel Technologies Palaiseau France

We introduce the HyperC language, a data parallel extension of C intended for portability over a wide range of architectures. We present the main topics of the language: the explicit parallelism through the data, the synchronous semantics and the parallel flow control that allows asynchronous execution, new function qualifiers to emphasize locality properties code and, finally, new communication techniques to allow overlap of communications and computations even for irregular computations. All these features are discussed with respect to portability and code reusability issues.< >

关键词： parallel programming Concurrent computing Communication system control Computer architecture parallel processing Data flow computing Hardware programming profession Topology Equations

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