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international Workshop on Unifying Theory and Practice in Distributed Systems, 1994

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international Workshop on Unifying Theory and Practice in Distributed Systems, 1994

ISBN: (纸本)3540600426

The proceedings contain 17 papers. The special focus in this conference is on Experimental systems and Group communication. The topics include: Architectural issues in the stormcast system;lessons learned from building and using the arjuna distributed programming system;a high performance totally ordered multicast protocol;new applications for group computing;support for information sharing in CSCW based on causally and totally ordered group communication;the design of the transis system;the rampart toolkit for building high-integrity services;deriving optimal checkpoint protocols for distributed shared memory architectures;transaction model vs virtual synchrony model;towards open service environments;correctness proofs of distributed algorithms;deterministic fault injection of distributed systems;a non-blocking lightweight implementation of causal order message delivery;merits of a probabilistic approach to properties in process group systems;sequential consistency in distributed systems and speedup limits for tightly-coupled parallel computations.

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Integrated VLSI layout compaction and wire balancing on a shared memory multiprocessor: evaluation of a parallel algorithm

Integrated VLSI layout compaction and wire balancing on a sh...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： R.P. Chalasani K. Thulasiraman M.A. Corneau Department of Electrical & Computer Engineering Concordia University Montreal Canada Department of Computer Science University of Oklahama Norman OK USA

We first present a unified formulation to three problems in VLSI physical design: layout compaction, wire balancing and integrated layout compaction and wire balancing problem. The aim of layout compaction is to achieve minimum chip width. Whereas wire balancing seeks to achieve minimum total wire length, integrated layout compaction and wire balancing seeks to minimize wire length maintaining the chip width at the optimum value. Our formulation is in terms of the dual transshipment problem. We then review our recent work on a parallel algorithm for the dual transshipment problem. We show how this algorithm called Modified Network Dual Simplex Method provides a unified approach to solve the three problems mentioned above and present experimental results. Our implementations have been on the BBN Butterfly machine. We draw attention to certain rather unusual results and argue that if the MNDS method is used then integrated layout compaction and wire balancing will achieve minimum chip width and a total wire length close to the optimum achieved by the wire balancing algorithm.< >

关键词： Very large scale integration Compaction Wire Circuits parallel algorithms Design automation Process design parallel processing Network topology Physics computing

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Recursive circulant: a new topology for multicomputer networks (extended abstract)

Recursive circulant: a new topology for multicomputer networ...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Jung-Heum Park Kyung-Yong Chwa Coding Technology Department Electronics and Telecommunications Research Institute Taejon South Korea Department Computer Science KAIST Taejon South Korea

ISBN: (纸本)0818665076

We propose a new topology for multicomputer networks, called recursive circulant. Recursive circulant G(N, d) is defined to be a circulant graph with N nodes and jumps of powers of d, d/spl ges/2. G(N, d) is node symmetric, has a hamiltonian cycle unless N/spl les/2, and can be recursively constructed when N=cd/sup m/, 1/spl les/c/spl les/d. We analyze various network metrics of G(cd/sup m/, d) such as connectivity, diameter, mean internode distance, visit ratio, and develop a shortest path routing algorithm in G(cd/sup m/, d). G(2/sup m/, 4), whose degree is m, compares favorably to the hypercube Q/sub m/. G(2/sup m/, 4) has the maximum connectivity, and its diameter is [(3m-1)/4]. A simple broadcasting algorithm in G(2/sup m/, 4) is also presented.< >

关键词： Network topology Algorithm design and analysis Hypercubes Computer science Routing Drives Communication system control parallel architectures

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A parallel algorithm for the single step searching problem

A parallel algorithm for the single step searching problem

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： J.S. Lin F.R. Hsu R.C.T. Lee Department of Computer Science National Tsing Hua University Hsinchu Taiwan Department of Accounting Providence University Taichung Taiwan Providence University Taichung Taiwan

Introduces the single-step searching problem, which is defined as follows. We are given a graph where each vertex is associated with a weight. Assume that every edge of graph is of equal length. A fugitive may be hidden in any edge. We are asked to assign searchers to vertices to search the entire graph in one step such that no fugitive can escape. The cost of a searching plan is related to the weights of the vertices in which the searchers are initially located. Our goal is to minimize the cost of the searching plan. A parallel algorithm based upon The EREW model is proposed to solve this problem. This algorithm applies the tree contraction technique. The critical point is that we have to transform a general tree into a binary tree, including pseudo-nodes, in order to apply this tree contraction technique. A new algorithm is devised to solve the problem on the transformed binary tree. It can be proved that this new algorithm is correct, as it produces a correct solution for the original tree. Our algorithm has an optimal speed-up.< >

关键词： parallel algorithms Tree graphs Algorithm design and analysis Costs Binary trees Computational modeling Concurrent computing Process design Computer science parallel processing

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Cenju-3 parallel computer and its application to CFD

Cenju-3 parallel computer and its application to CFD

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： K. Muramatsu Shun Doi T. Washio T. Nakata Computer System Research Laboratory C&C Research Laboratory NEC Corporation Limited Kawasaki Kanagawa Japan

The exploitation of the effectiveness of parallel computers for computational fluid dynamics (CFD) requires an efficient parallel algorithm for numerical solution of the Navier-Stokes equations. This paper discusses the parallelization of an incompressible Navier-Stokes equation solver, and its implementation to the Cenju-3 parallel computer. We mainly focus our attention to the parallel solution of the discrete Poisson equations, which solution consumes the most of the computational time. Two parallel linear solvers are implemented based on a Rectangular Domain Decomposition Method (RDDM) and on the SMAC scheme. A parallel linear solver implemented is the Blocked MICCG (B-MICCG) method introduced by Washio and Hayami. The other linear solver is the Multi-Grid preconditioned Bi-CGSTAB(MG-Bi-CGSTAB) method. Numerical experiments has been conducted on Cenju-3 for up to 25 processors. Although the MG-Bi-CGSTAB method produces poorer speedup than the B-MICCG method, the MG-Bi-CGSTAB method is about 4 times faster than the B-MICCG method in terms of the total execution time.< >

关键词： Computer applications Concurrent computing Application software Computational fluid dynamics Navier-Stokes equations Poisson equations Distributed computing Computer networks Laboratories National electric code

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Performance of 4-dimensional PANDORA networks

Performance of 4-dimensional PANDORA networks

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： R. Holt A.B. Ruighaver Department of Computer Science University of Melbourne Parkville Australia

The Melbourne University Optoelectronic Multicomputer Project is investigating dense optical interconnection networks capable of providing low latency data transfers of small data items. Such capabilities are useful in the exploitation of small grain parallelism. In many cases, reducing the grain size of tasks increases the amount of parallelism which can be found in the program. Our networks use an organization of data transfers called PANDORA (parallel Newscasts on a Dense Optical Reconfigurable Array). The communication patterns on a PANDORA network are pre-determined, removing the overhead of sending and decoding addressing information. Instead the data is recognized by the time of arrival and the channel on which it arrives. Previous efforts have focused on 2-dimensional multiple broadcasting networks where each node may broadcast a different data item on the row and columns of the network. For large processor arrays, we have to reduce the density of the interconnection network as full interconnection on each row becomes too expensive. This paper discusses a 4-dimensional network which achieves a significant reduction in density with only a small increase in data transfer delays.< >

关键词： Broadcasting Optical fiber networks Optical arrays Application software Optical interconnections Multiprocessor interconnection networks Delay parallel processing Computer science Grain size

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Architectural issues in designing heterogeneous parallel systems with passive star-coupled optical interconnection

Architectural issues in designing heterogeneous parallel sys...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： R. Prakash D.K. Panda Department of Computer and Information Science Ohio State Uinversity Columbus OH USA

This paper investigates architectural and communication issues in designing heterogeneous parallel systems. The emerging high speed passive star-coupled optical interconnection using wavelength division multiplexing is considered as the system interconnect to provide high bandwidth communication demanded by heterogeneous systems. A representative master-slave computational model together with two different task scheduling strategies are used to evaluate and determine suitable communication strategy for such systems. It is shown that a hierarchical ALOHA-based communication strategy between the master and the slaves, implemented on top of the passive star-coupled network, leads to a considerable reduction in contention and task completion time compared to the direct communication from the slaves to the master. The time division multiplexed access (TDMA) approach has performance comparable to the hierarchical strategy. Depending on the application characteristics, the number of levels in the hierarchal scheme can be chosen to provide a balance between channel contention and overall execution time. These results provide guidelines for designing scalable heterogeneous systems in near future.< >

关键词： Optical design Master-slave Computational modeling Optical interconnections Concurrent computing Application software Distributed computing Scheduling High speed optical techniques Wavelength division multiplexing

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A systolic array implementation of common factor algorithm to compute DFT

A systolic array implementation of common factor algorithm t...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Shousheng He M. Torkelson Department of Applied Electronics Lund University Lund Sweden

An extension to the common factor algorithm, CFA, to compute discrete Fourier transform, DFT, under the condition that the site of the transform is N=M/sup 2/, shows that the input and output data array of the transform may have identical index mapping. A simple planar 2-dimensional systolic array implementation of CFA algorithm is presented. The systolic array consists of N homogeneous processing element, PE. A DFT of size N=M/sup 2/ can be computed in 2M+1 steps of pipelined operations, achieving the area-time complexity AT/sup 2/=O(N/sup 2/log/sup 3/N). Asymptotically sub-optimal and without the necessity of complicated index mapping and data shuffling, the proposed approach is compared favorably with other existing approaches in realistic VLSI implementation. This architecture has also very good expansibility that a 2/sup t/N-size DFT transform can be computed on 2/sup t/ nearest-neighbor connected N-size array with reloaded twiddle factors, which makes it more suitable for VLSI implementation of DFT transform in various practical size.< >

关键词： Systolic arrays Discrete Fourier transforms Very large scale integration Signal processing algorithms Fourier transforms High performance computing parallel algorithms Helium Computer architecture Signal processing

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Mathematic-physical engine: parallel processing for modeling and simulation of physical phenomena

Mathematic-physical engine: parallel processing for modeling...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： V.K. Jain A.D. Snider Department of Electrical Engineering University of South Florida Tampa FL USA

Mathematical modeling of various physical phenomena, ranging from fluid flow to electromagnetic field dynamics, from thermal patterns inside a semiconductor wafer to thermal patterns on a geophysical scale, and from combustion inside an automotive cylinder to ion transport across a biological membrane, is a challenge for the 1990s and beyond. These processes share in common a basic underlying structure in that they are described by systems of partial differential equations. This paper proposes parallel processing concepts for the real time simulation of such physical phenomena. Specifically we present a mathematic-physical engine (MPE) to solve in real time, and to display three-dimensionally, the solution of sets of ordinary or partial differential equations. In fact, different versions of the MPE are discussed ranging from a single commercial parallel machine, to networked supercomputers, to a stacked-wafer dedicated machine to suit the needs of scientists/engineers around the world. High speed networking is proposed for remote usage of an expensive MPE facility. Such a capability can enhance the ability of scientists and engineers to accelerate basic research on the one hand, and product development on the other.< >

关键词： Engines parallel processing Mathematical model Biological system modeling Partial differential equations Semiconductor device modeling Fluid flow Electromagnetic fields Fluid dynamics Vehicle dynamics

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Building a better butterfly: the multiplexed metabutterfly

Building a better butterfly: the multiplexed metabutterfly

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： F.T. Chong E.A. Brewer F.T. Leighton T.F. Knight Massachusetts Institute of Technology

Multistage networks are important in a wide variety of applications. Expander-based networks, such as multibutterflies, are a tremendous improvement over traditional butterflies in both fault and congestion tolerance. However, multibutterflies cost at least twice as much in chips and wiring as butterflies. It is also impossible to build large multibutterflies due to their wiring complexity. We show that we can build an expander-based network that has comparable cost to a butterfly with the same number of endpoints, yet has substantially better fault and congestion performance. Specifically, we introduce a hierarchical construction that dramatically reduces wiring complexity and makes large expanders buildable. We are able to exploit the hierarchical structure to find large numbers of logical wires to multiplex over a smaller number of physical wires. Since many of the wires in an expander-based network are used to provide alternate paths, not useful bandwidth, substantial multiplexing can be done without significantly degrading performance. We present simulation results to support our conclusions. In comparing a butterfly with the comparable 2-to-1 multiplexed metabutterfly, we found that the metabutterfly performed better by nearly a factor of two on random traffic and greater than a factor five on worst-case traffic.< >

关键词： Wires Wiring Costs Fault tolerance Bandwidth Multiprocessor interconnection networks Contracts Large scale integration Logic parallel architectures

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