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Digital Circuit Testing on a Network of Workstations

Digital Circuit Testing on a Network of Workstations

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international Conference on parallel Processing (ICPP)

作者： S. Srinivasan J.H. Aylor Center for Semicustom Integrated Circuits Department of Electrical Engineering University of Virginia Charlottesville USA

This paper presents preliminary results of research being conducted in the application of distributed/parallel algorithms to automatic test pattern generation for synchronous sequential circuits. The system is required to be portable across a wide variety of architectures -from workstations to dedicated parallel machines. This requirement necessitates the use of a parallel programming environment that provides a layer of abstraction between the application and the hardware. The first phase of the proposed system involves generation of circuit covers - input patterns that control the circuit outputs.

关键词： Program processors Test pattern generators parallel processing Circuit faults Sequential circuits Runtime Cluster computing

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Transparent fault tolerance for distributed Ada applications

Transparent fault tolerance for distributed Ada applications

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1994 Annual international Conference on TRI-Ada 1994

作者： Breland, Mark A. Rogers, Steven A. Nelson, Kenneth L. Brat, Guillaume P. 3500 West Balcones Center Drive AustinTX78759 United States Computing Devices International 8800 Queen Avenue South BloomingtonMN55431 United States Department of Electrical and Computer Engineering University of Texas at Austin AustinTX78712 United States

ISBN: (纸本)0897916662

The advent of open architectures and initiatives in massively parallel supercontputing, combined with the maturation of distributed processing methods and algorithms, has enabled the implementation of ~esponsive so~are-based fault tolerance. Expanding capabilities of distributed Ada runtime environments firther stimulate the incorporation of hardware fault tolerance into critical, realtime embedded systems. Through the integration of proven Ada program component distribution and virtually synchronous convnunication protocols, we have established a benchmark fault tolerant system, which layers transparently between an Ada application and the runtime environment. Such transparence allows rapid reconfiguration of distribution and fault tolerance characteristics without change to the source code, thus enhancing portability, scalability, and reuse. The Ada Fault Tolerance project has implemented sojhvare technologies which penetrate the envelope of an Ada program to detect, diagnose, and recover from hardware faults. These realtime facilities interact with the Rational distributed application development and runtime environment systernx to service replicated Ada sojlware tasks (i.e., threads of control). The deployed system proves that all replicated threads, including those of independently dis~ibuted components, can achieve timely consensus during periodic fault detection cycles through transparently embedded voting protocols. Our implementation uses a hybrid redundancy computation strategy and relies on a communication layer which provides virtual synchrony via a causal multicast protocol. © 1994 ACM.

关键词： Fault tolerance

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parallel evaluation of a parallel architecture by means of calibrated emulation

Parallel evaluation of a parallel architecture by means of c...

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international symposium on parallel Processing

作者： H.L. Muller P.W.A. Stallard D.H.D. Warren S. Raina Department of Computer Science University of Bristol Bristol UK

A parallel transputer-based emulator has been developed to evaluate the Data Diffusion Machine (DDM)/spl minus/a highly parallel virtual shared memory architecture. The emulator provides performance results of a hardware implementation of the DDM using a calibrated virtual clock. Unlike the virtual clock of a simulator, the emulator clock is bound to a fixed fraction of real time, so individual processors may time actions independently without the need for a global clock value. Each component of the emulator is artificially slowed down, so that the balance of the speeds of all components reflects the balance of the expected hardware implementation. The calibrated emulator runs an order of magnitude faster than a simulator (the application program is executed directly and there is no overhead for the maintenance of event lists) and, more importantly, the emulator is inherently parallel. This results in a peak emulation speed of 27 MIPS when simulating a machine with 81 leaf nodes on a 121-node transputer system.< >

关键词： parallel architectures Emulation Distributed decision making Clocks Memory architecture Software prototyping Hardware Virtual prototyping Prototypes programming profession

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Bounds on the number of passes in multistage interconnection networks

Bounds on the number of passes in multistage interconnection...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Y.R. Potlapalli D.P. Agrawal Department of Electrical and Computer Engineering North Carolina State University Raleigh NC USA

Determining the exact number of passes required to realize a permutation on a multistage interconnection network (MIN) is known to be an /spl Nscr//spl Pscr/ Complete problem. We present a new characteristic of conflicts in MINs which makes conflict detection easier. We use this important property to develop a polynomial time algorithm to determine strong upper and lower bounds on the number of passes required to realize a permutation.< >

关键词： Intelligent networks Multiprocessor interconnection networks Genetic mutations Upper bound parallel architectures parallel algorithms Routing Switches Polynomials Testing

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CCL: a portable and tunable collective communication library for scalable parallel computers

CCL: a portable and tunable collective communication library...

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international symposium on parallel Processing

作者： V. Bala J. Bruck R. Cypher P. Elustondo A. Ho Ching-Tien Ho S. Kipnis M. Snir Kendall Research Corporation Waltham WA USA IBM Research Division Almaden Research Center San Jose CA USA IBM Research Division IBM Thomas J. Watson Research Center Yorktown Heights NY USA IBM Argentina Ing. Buenos Aires Argentina IBM Israel Science and Technology Center Haifa Israel

A collective communication library for parallel computers includes frequently used operations such as broadcast, reduce, scatter, gather, concatenate, synchronize, and shift. Such a library provides users with a convenient programming interface, efficient communication operations, and the advantage of portability. A library of this nature, the collective communication library (CCL), intended for the line of scalable parallel computer products by IBM, has been designed. CCL is part of the parallel application programming interface of the recently announced IBM 9076 Scalable POWERparallel System 1 (SP1). We examine several issues related to the functionality, correctness, and performance of a portable collective communication library while focusing on three novel aspects in the design and implementation of CCL: (i) the introduction of process groups, (ii) the definition of semantics that ensures correctness, and (iii) the design of new and tunable algorithms based on a realistic point-to-point communication model.< >

关键词： Libraries Concurrent computing Portable computers Broadcasting Application software parallel programming Scattering Computer interfaces Runtime Algorithm design and analysis

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parallel processing of fuzzy inferences

Parallel processing of fuzzy inferences

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international symposium on Multiple-Valued Logic

作者： C. Moraga J. Canas R. Monge L. Salinas M. Gomez Department of Computer Science University of Dortmund Dortmund Germany Departmento de Informática Universidad Tècnica Federico Santa Maria Valparaiso Chile Departmento de Matemática Universidad Tècnica Federico Santa Maria Valparaiso Chile

Rule based systems are computationally very demanding, since a large number of rules has to be evaluated every time new input data are observed in order to undertake a corresponding action. The authors study the possible improvements in performance by using parallel processing. Both fine grade algorithms and standard multiprocessor architectures for Mamdani-type fuzzy systems with two inputs and one output are considered. It is shown, that a speed-up close to linear may be achieved. The results may be extended to systems with more than two inputs.< >

关键词： parallel processing Fuzzy logic Fuzzy systems Fuzzy sets Inference algorithms Bismuth Computer architecture Computer science Knowledge based systems Electrical equipment industry

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A class of scalable architectures for high-performance, cost-effective parallel computing

A class of scalable architectures for high-performance, cost...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： S.G. Ziavras Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ USA

The family of reconfigurable generalized hypercube (RGH) architectures is proposed for the construction of scalable parallel computers. The objective is to reduce the high VLSI complexity of generalized hypercubes while maintaining to high extent their outstanding performance. Generalized hypercubes are versatile topologies of very high cost that optimally emulate binary hypercubes and k-ary n-cubes. RGH's, which are lower-cost reconfigurable systems, emulate efficiently generalized hypercubes for application algorithms that use regular communication patterns. RGH's generally perform better than binary hypercubes and k-ary n-cubes with the same number of nodes. To illustrate the viability of RGH's, extensive cost analysis and comparisons with relevant systems are carried out. The hardware cost of RGH's is shown to be even lower than that of fat trees. Therefore, scalable RGH's are viable candidates for the construction of versatile parallel computers.< >

关键词： Computer architecture parallel processing Hypercubes Very large scale integration Topology Concurrent computing Cost function Emulation Nearest neighbor searches Hardware

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Multi-dimensional radiative transfer computations using a scalable parallel implementation of the discrete-ordinates method

Multi-dimensional radiative transfer computations using a sc...

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IEEE international symposium on Geoscience and Remote Sensing (IGARSS)

作者： J.L. Haferman T.F. Smith W.F. Krajewski Mechanical Engineering University of Iowa Iowa IA USA Civil and Environmental Engineering Center for Global and Regional Environmental Research University of Iowa Iowa IA USA

A scalable parallel implementation of the discrete-ordinates method for the solution of the radiative transfer equation is discussed. The approach presented uses a parallel architecture to solve the radiative transfer equation in three-dimensional Cartesian geometries. Two numerical experiments are presented. The first examines the effect of grid size and number of processors on computational time for a given problem, whereas the second experiment examines the effect of quadrature order on computation times. For both experiments, the parallel algorithm is used to compute upwelling brightness temperatures from a precipitating cloud. Using the parallel model, brightness temperature fields for three-dimensional precipitating atmospheres can be computed much more quickly than by a serial model.< >

关键词： Equations Grid computing Concurrent computing Brightness temperature Atmospheric modeling parallel architectures Geometry parallel algorithms Cloud computing Atmosphere

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Evaluation and measurement of multiprocessor latency patterns

Evaluation and measurement of multiprocessor latency pattern...

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international symposium on parallel Processing

作者： Xiaodong Zhang Yong Yan Keqiang He High Performance Computing and Software Laboratory University of Texas San Antonio San Antonio TX USA

ISBN: (纸本)0818656026

Network latency, the delay caused by communication between processors and memory modules over the network in a multiprocessor system, is a major source of degraded parallel computing performance. We first give an overview of an experimental metric which uses network latency to measure and evaluate the scalability of parallel programs and architectures. We put emphasis on evaluation of latency sources and their methods in program execution. We report experimental results of evaluating the scalability of several scientific computing algorithms on the KSR-1. In comparison, we also present preliminary experiments on the CM-5 multicomputer architecture. Our comparisons indicate that the CM-5 has less network latency effects and is a more scalable architecture the the KSR-1. The analyses and experiments show that the latency metric is an important method to effectively measure overheads inherent in the program and the architecture for parallel computing scalability evaluation.< >

关键词： Scalability parallel processing Computer architecture Delay effects Laboratories Multiprocessing systems Size measurement Multiprocessor interconnection networks Helium High performance computing

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ControlH: a fourth generation language for real-time GN&C applications

ControlH: a fourth generation language for real-time GN&C ap...

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IEEE international symposium on Computer Aided Control System Design (CACSD)

作者： M. Englehart M. Jackson Honeywell Technology Center Minneapolis MN USA

Describes the defining characteristics of the language ControlH. ControlH is being designed under the ARPA DSSA (Domain Specific Software architectures) Program. ControlH is designed for describing guidance, navigation and control (GN&C) algorithms in a concise yet rigorous manner. The language objects, structure, data types, and operations have been tailored to the domain of GN&C algorithm specification. The language also provides hooks for optimization of the software produced from the specification. A translator has been developed which generates high-quality, modular Ada, based on ControlH specifications. The language and the translator are used to provide software reuse and configuration at the high level of GN&C algorithm specification.< >

关键词： Application software Decision support systems Software architecture Navigation Automatic control programming profession Automatic programming Algorithm design and analysis Software algorithms Computer architecture

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