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检索条件"任意字段=International Symposium on Parallel Architectures, Algorithms, and Programming"

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A language for conveying the aliasing properties of dynamic, pointer-based data structures

A language for conveying the aliasing properties of dynamic,...

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international symposium on parallel Processing

作者： J. Hummel L.J. Hendren A. Nicolau Department of Computer Science University of California Irvine Irvine CA USA School of Computer Science McGill University Montreal QUE Canada

High-performance architectures rely upon powerful optimizing and parallelizing compilers to maximize performance. Such compilers need accurate program analysis to enable their performance-enhancing transformations. In the domain of program analysis for parallelization, pointer analysis is a difficult and increasingly common problem. When faced with dynamic, pointer-based data structures, existing solutions are either too limited in the types of data structures they can analyze, or require too much effort on the part of the programmer. In this paper we present a powerful description language for expressing the aliasing properties of dynamic date structures. Such descriptions provide the compiler with better information during alias analysis, and require only minimal effort from the programmer. Ultimately, this enables a more accurate program analysis, and an increased application of performance-enhancing transformations.< >

关键词： Data structures Program processors programming profession Performance analysis Information analysis Computer science Optimizing compilers parallel processing Sparse matrices Circuits

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On the effectiveness of residue code checking for parallel two's complement multipliers

On the effectiveness of residue code checking for parallel t...

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international symposium on Fault-Tolerant Computing (FTCS)

作者： U. Sparmann S.M. Reddy Computer Science Department University of Saarland Germany Department of Elect. and Comp. Engineering University of Iowa Iowa IA USA

The effectiveness of residue code checking for on-line error detection in parallel two's complement multipliers has up to now only been evaluated experimentally for few architectures. In this paper a formal analysis is given for most of the current multiplication schemes. Based on this analysis it is shown which check bases are appropriate, and how the original scheme has to be extended for complete error detection at the input registers and Booth recording circuitry. In addition, we argue that the hardware overhead for checking can be reduced by approximately one half if a small latency in error detection is acceptable. Schemes for structuring the checking logic in order to guarantee it to be self-testing, and thus achieve the totally self-checking goal for the overall circuit, are also derived.< >

关键词： Hardware Delay Computer errors Rails Computer science Registers Logic circuits Built-in self-test parallel algorithms Concurrent computing

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Performance of digital neuro-computers

Performance of digital neuro-computers

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Proceedings of the international Conference on Microelectronics for Neural Networks and Fuzzy Systems

作者： T. Cornu P. Ienne MANTRA Centre for Neuro-Mimetic Systems IN-F Ecublens Swiss Federal Institute of Technology Lausanne Switzerland

This paper deals with performance measurement and evaluation of digital neuro-computers. We discuss the constraints introduced by hardware implementations. A revisited definition of computer speed-up is then proposed, taking into account both the traditional notion of parallelization speed-up and the algorithmic precision of the machines. Finally we show, on the example of the Kohonen feature map algorithm, how a fair benchmarking procedure can be established to evaluate digital neuro-computers more significantly than using the traditional Mcups metric.

关键词： Hardware Artificial neural networks Signal processing algorithms Concurrent computing parallel programming Floating-point arithmetic Measurement Software libraries Signal processing parallel architectures

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Dynamic space warping algorithms on fine-grain array processors

Dynamic space warping algorithms on fine-grain array process...

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international symposium on parallel Processing

作者： Heung-Nam Kim M.J. Irwin R.M. Owens Chen-Mi Wu Department of Computer Science and Engineering Pennsylvania State University University Park PA USA Department of Engineering Technology National Taiwan Institute of Technology Taipei Taiwan

We present a new mapping strategy of the dynamic space warping algorithm (DSWA) onto a micro-grained array processor (MGAP). This new mapping strategy reduces the communication complexity between processing elements and increases the performance due to data pipelining and interleaving. The DSWA, which can be applied to image recognition, originally needs a four-dimensional array. Practically however, this four-dimensional algorithm must be mapped onto a two-dimensional array processor. A previous mapping used O(NW) processors to compute the distance between an N/spl times/N input image and a reference image with the warping distance W in O(NW) time. The new mapping scheme uses O(N/sup 2/) processors to generate each computation result in O(N+W/sup 2/) time. We also show the experimental results and performance comparison between Connection Machine (CM) 200 and the MGAP.< >

关键词： Heuristic algorithms Space technology Pipeline processing Very large scale integration Interleaved codes Image recognition Dynamic programming Computer science Complexity theory Image coding

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The Multicomputer Toolbox/spl minus/first-generation scalable libraries

The Multicomputer Toolbox/spl minus/first-generation scalabl...

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Annual Hawaii international Conference on System Sciences (HICSS)

作者： Skjellum Leung Smith Falgout Still Baldwin Computer Science Department & NSF Engineering Research Center Mississippi State University MS USA Northeast Parallel Architectures Center Syracuse University USA Numerical Mathematics Group Lawrence Livemore National Laboratory UK University of Illinois Urbana-Champaign USA

"First-generation" scalable parallel libraries have been achieved, and are maturing, within the Multicomputer Toolbox. The Toolbox includes sparse, dense, iterative linear algebra, a stiff ODE/DAE solver, and an open software technology for additional numerical algorithms. We have devised C-based strategies for useful classes of distributed data structures, including distributed matrices and vectors. The underlying Zip code message passing system has enabled process-grid abstractions of multicomputers, communication contexts, and process groups, all characteristics needed for building scalable libraries, and scalable application software. A data-distribution-independent approach to building scalable libraries is needed so that applications do not unnecessarily have to redistribute data at high expense. We discuss the strategy used for implementing data-distribution-independent mappings. We also indicate that data-distribution-independent algorithms are sometimes more efficient than fixed-data-distribution counterparts, because redistribution of data can be avoided, and that this question is strongly application dependent.< >

关键词： parallel machines parallel programming Distributed computing Data structures Linear algebra

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A formal approach to pipeline optimization in synthesis of digital signal processors with fine grain parallelism

A formal approach to pipeline optimization in synthesis of d...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： S. Zimmermann E. Lueder Institut f. Netzwerk-U. Systemtheorie Universität Stuttgart Stuttgart Germany

In this paper we present a constraint-model for pipelined digital signal processors, based on mathematical programming. Our intention is to maximize the utilization of allocated hardware components by minimizing the clock-cycle time and the period of cyclic innermost loop schedules in one approach. The constraint formulations are developed for a very general multiphase clocking environment with an FPGA (Field Programmable Gate Array) target architecture.< >

关键词： Signal synthesis Digital signal processors Clocks Hardware Field programmable gate arrays Signal processing algorithms Mercury (metals) Delay Pipeline processing parallel processing

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Comparison of three different architectures for MOS-compatible quadratic synapses

Comparison of three different architectures for MOS-compatib...

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international symposium on Speech, Image Processing and Neural Networks

作者： S.M. Fakhraie K.C. Smith J.M. Xu Department of Electrical and Computer Engineering University of Toronto Toronto ONT Canada Department of Electrical and Electronics Engineering Hong Kong University of Science and Technology Hong Kong China

Inspired by the harmony between the basic functional elements of biological neural networks and their natural operating media, we have been seeking for ways to implement artificial neural networks (ANNs) using the intrinsic functionality of the most commonly available devices in an electronics technology, in contrast to the method of hardware-compilation of software-simulation modules. In the case of MOS technology, we employ a quadratic functional equation similar to that found in standard MOS transistors to implement synapses in ANNs. A structure has been proposed in to implement a MOS device with externally-controllable threshold voltage to be employed as a synapse. In the present work, we develop and compare practical architectures within which these synapses can be utilized optimally. A simulator and proper training algorithms have been developed to simulate different hardware-based architectures.< >

关键词： Equations Computer architecture MOSFETs Threshold voltage Artificial neural networks MOS devices parallel processing Hardware Voltage control CMOS technology

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Time-parallel computational strategy for FDTD solution of Maxwell's equations

Time-parallel computational strategy for FDTD solution of Ma...

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Antennas and Propagation Society international symposium

作者： M.A. Jensen A. Fijany Y. Rahmat-Samii Department of Elec Engineering UCLA Los Angeles CA USA JPL California Institute of Technology Pasadena CA USA

A major emphasis within the computational electromagnetics (CEM) community concerns the solution of Maxwell's differential equations using finite-difference time-domain (FDTD) techniques. Because of the computational time and memory requirements associated with these time-stepping algorithms, their application to very large problems has been somewhat limited. To alleviate these computational obstacles, some efforts have previously been aimed at the implementation of space-parallelism-the concurrent computation of unknowns at different points in the spatial mesh using multiple processors-in the FDTD algorithms. For these schemes, however, communication and synchronization requirements have limited the amount of computational speed-up provided by the use of additional processors. This limited potential for enhanced computational efficiency implies that if full exploitation of the capabilities of emerging multiple instruction multiple data (MIMD) architectures is to be realized, approaches must be developed which represent a drastic departure from traditional FDTD techniques. The aim of the paper is to present such a computational strategy. Unlike traditional approaches which use space-parallelism this methodology exploits the decoupling mechanism of an eigenvalue-eigenvector (EE) decomposition of the FDTD matrix to allow the efficient implementation of time-parallelism-the simultaneous computation of field values at multiple time steps. The resulting algorithm is highly coarse grain and has minimum communication and synchronization requirements.< >

关键词： Finite difference methods Time domain analysis Maxwell equations Matrix decomposition Concurrent computing Laplace equations Sparse matrices Differential equations Computational efficiency Computer architecture

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Industrial presentation. KSRI. High performance and ease of programming, no longer an oxymoron

Industrial presentation. KSRI. High performance and ease of ...

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Proceedings of the 5th Annual ACM symposium on parallel algorithms and architectures

作者： Frank, Steve

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parallelizing algorithms for symbolic computation using ||MAPLE|| 93

Parallelizing algorithms for symbolic computation using ||MA...

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4th ACM SIGPLAN symposium on Principles and Practice of parallel programming, PPOPP 1993

作者： Siegl, Kurt Johannes Kepler University LinzA-4040 Austria

ISBN: (纸本)0897915895

||MAPLE|| (speak: parallel Maple) is a portable system for parallel symbolic computation. The system is built as an interface between the parallel declarative programming language Strand and the sequential computer algebra system Maple, thus providing the elegance of Strand and the power of the existing sequential algorithms in Maple. The implementation of difFerent parallel programming paradigms shows that it is fairly easy to parallelize even complex algebraic algorithms using this system. Sample applications (among them algorithms solving multivariate nonlinear equation systems) are implemented on various parallel architectures. For example a straightforward parallelization of the complex and important problem of real root isolation has been parallelized using a generic Strand program of fewer than 20 Unes of code and a slight modification of 5 lines in the original sequential Maple source. Even with such a simple modification we gained a speed-up of 5 times, that is better than those reported by others in the literature.

关键词： Logic programming

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