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programming a distributed system using shared objects 2

Programming a distributed system using shared objects

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2nd international symposium on High Performance Distributed Computing, HPDC 1993

作者： Tanenbaum, A.S. Bal, H.E. Kaashoek, M.F. Dept. of Math. and Comput. Sci. Vrije Univ. Amsterdam Netherlands Laboratory for Computer Science M.I.T CambridgeMA United States

ISBN: (纸本)0818639008

Building the hardware for a high-performance distributed computer system is a lot easier than building its software. The authors describe a model for programming distributed systems based on abstract data types that can be replicated on all machines that need them. Read operations are done locally, without requiring network traffic. Writes can be done using a reliable broadcast algorithm if the hardware supports broadcasting;otherwise, a point-to-point protocol is used. The authors have built such a system based on the Amoeba microkernel, and implemented a language, Orca, on top of it. For Orca applications that have a high ratio of reads to writes, they measure good speedups on a system with 16 processors. © 1993 IEEE.

关键词： Computer hardware

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Heuristics for mapping parallel computations to heterogeneous parallel architectures 7

Heuristics for mapping parallel computations to heterogeneou...

引用

1993 Workshop on Heterogeneous Processing, VVHP 1993, Held in conjunction with the 7th international parallel Processing symposium

作者： Tao, L. Narahari, B. Zhao, Y.C. Dept. of CS Concordia University MontrealQC Canada Dept. of EE and CS George Washington University WashingtonDC20052 United States

ISBN: (纸本)0818635312

This paper studies the problem of allocating the interacting task modules, of a parallel program, to the heterogeneous processors in a parallel architecture. The goal is to provide a load balanced allocation which minimizes the completion time of the program. The problem of finding an optimal allocation is known to be an NP-hard problem, even if the processors are homogeneous, and thus necessitates development of heuristic schemes. This paper presents three heuristic algorithms for task assignment, based on simulated annealing, tabu search, and stochastic probe approaches respectively. We present an experimental analysis of these three heuristics and compare their performance. Experiments reveal that our new stochastic probe approach always yields the best solutions while requiring significantly less CPU time. © 1993 IEEE.

关键词： Probes

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Strategies for mapping Lee's maze routing algorithm onto parallel architectures 7

Strategies for mapping Lee's maze routing algorithm onto par...

引用

7th international parallel Processing symposium, IPPS 1993

作者： Yen, I.-L. Dubash, R.M. Bastani, F.B. Dept. of Comput. Sci. Michigan State Univ. East LansingMI48824-1027 United States Department of Computer Science University of Houston HoustonTX77204-3475 United States

ISBN: (纸本)0818634421

Lee's (1961) maze-routing algorithm has been a popular method for routing wires in VLSI circuits. It can also be applied to a variety of other problems, such as robot path planning. Although the algorithm is simple and easy to implement, its computation time can be quite high. Therefore, it is a very attractive candidate for implementation on parallel systems. The major issue in parallelizing this algorithm is mapping the grid space of the problem to the processor space. The communication cost and processor utilization can be greatly affected by the mapping strategy used. Won and Sahni (1987) have studied a class of mapping strategies for Lee's algorithm and analyzed their performance. The authors propose two new mapping strategies. First, they modify Won and Sahni's mapping algorithm by using the concept of mirror images to allow higher processor utilization while reducing the number of boundary cells. The new algorithm is shown to be better than the original one in an obstacle-free grid space. Then, they propose a dynamic mapping algorithm. This new mapping algorithm is shown to give an optimal mapping in an obstacle-free grid space. Also, they performed simulation to study the relative performance of these mapping algorithms for grid spaces with obstacles. The results show that the new algorithms are substantially faster than the earlier ones. © 1993 IEEE.

关键词： Motion planning

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Shared memory consistency conditions for non-sequential execution: Definitions and programming strategies 93

Shared memory consistency conditions for non-sequential exec...

引用

5th Annual ACM symposium on parallel algorithms and architectures, SPAA 1993

作者： Attiya, Hagit Chaudhuri, Soma Friedman, Roy Welch, Jennifer L. Department of Computer Science The Technion Haifa32000 Israel Laboratory for Computer Science Massachusetts Institute of Technology CambridgeMA02139 United States Department of Computer Science Iowa State University United States Department of Computer Science Texas A and M University College StationTX77843-3112 United States

ISBN: (纸本)0897915992

To enhance performance on shared memory multiprocessors, various techniques have been proposed to reduce the latency of memory accesses, including pipelining of accesses, out-of-order execution of accesses, and branch prediction with speculative execution. These optimizations however can complicate the user's model of memory. This paper attacks the problem of simplifying programming on two fronts. First, a general framework is presented for defining shared memory consistency conditions that allows non-sequential execution of memory accesses. The interface at which conditions are defined is between the program and the system, and is architecture-independent. The framework is used to generalize four known consistency conditions-sequential consistency, hybrid consistency, weak consistency, and release consistency-for non-sequential execution. Second, several techniques are described for structuring programs so that a shared memory that provides the weaker (and more efficient) condition of hybrid consistency appears to guarantee the stronger (and more costly) condition of sequential consistency. The benefit is that sequentially consistent executions are easier to reason about. The first and second techniques statically classify accesses based on their type. This approach is extremely simple to use and leads to a general methodology for writing efficient synchronization code. The third technique is to avoid data races in the program;this technique also works on a simple variant of release consistent hardware, with an appropriate change to the definition of data race. © 1993 ACM.

关键词： Memory architecture

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Efficient parallel mappings of a dynamic programming algorithm: A summary of results 7

Efficient parallel mappings of a dynamic programming algorit...

引用

7th international parallel Processing symposium, IPPS 1993

作者： Karypis, G. Kumar, V. Dept. of Comput. Sci. Minnesota Univ. MinneapolisMN55414 United States

ISBN: (纸本)0818634421

The authors are concerned with dynamic programming (DP) algorithms whose solution is given by a recurrence relation similar to that for the matrix parenthesization problem. Guibas, Kung and Thompson (1979), presented a systolic array algorithm for this problem that uses O(n2) processing cells and solves the problem in O(n) time. The authors present three different mappings of this systolic algorithm on a mesh connected parallel computer. The first two mappings use commonly known techniques for mapping systolic arrays to mesh computers. Both of them are able to obtain only a fraction of maximum possible performance. The primary reason for the poor performance of these formulations is that different nodes at different levels in the multistage graph in the DP formulation require different amounts of computation. Any adaptation has to take this into consideration and evenly distribute the work among the processors. The third mapping balances the work load among processors and thus is capable of providing efficiency approximately equal to 1 (i.e., speedup approximately equal to the number of processors) for any number of processors and sufficiently large problem. They experimentally evaluate these mappings on a mesh embedded onto a 256 processor nCUBE/2. © 1993 IEEE.

关键词： Systolic arrays

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VMPP: a virtual machine for parallel processing

VMPP: a virtual machine for parallel processing

引用

international symposium on parallel Processing

作者： E.C. Loyot A.S. Grimshaw Department of Computer Science University of Virginia USA

In the field of parallel processing, there is a great diversity of languages and architectures which become obsolete at a rapid pace. In this environment, portability is an important issue. Unfortunately, most parallel languages are not portable. This portability problem can be solved using a virtual machine approach. In this approach, front-end translators translate various parallel source languages into code for a virtual machine. Back-end translators translate the virtual machine code into executable codes for a variety of parallel architectures. The Virtual Machine for parallel Processing (VMPP) is designed to provide portability for a variety of high-level parallel programming languages without significantly sacrificing performance.< >

关键词： Virtual machining parallel processing parallel programming Computer architecture parallel languages parallel architectures Concurrent computing Investments Writing Computer science

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Genie: An environment for partitioning and mapping in embedded multiprocessors

Genie: An environment for partitioning and mapping in embedd...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： S. Yalamanchili L. Te Winkel D. Perschbacher B. Shenoy Computer Systems Research Laboratory School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA Alliant Tech Systems Inc. Hopkins MN USA

Embedded multiprocessor architectures present different constraints, and therefore challenges to the problems of partitioning and mapping parallel programs. They must typically optimize throughput and/or latency while satisfying placement, memory, and processor throughput constraints. This paper describes the algorithms, organization, and application of Genie - a set of tools for the partitioning and mapping of parallel programs for embedded multiprocessor architectures under such constraints. At one end Genie is tightly coupled into a commercial software development environment - Teamwork SA/RT. At the other it presents an interface to simulation and modeling tools. A example is presented of the application of this environment to an existing real-time embedded application - autonomous underwater vehicle (AUV).< >

关键词： Computer architecture Application software Embedded computing Partitioning algorithms Throughput Software tools Teamwork programming Production Circuit simulation

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Mapping to reduce contention in multiprocessor architectures

Mapping to reduce contention in multiprocessor architectures

引用

international symposium on parallel Processing

作者： L. Schwiebert D.N. Jayasimha Department of Computer and Information Science Ohio State Uinversity Columbus OH USA

Reducing communication overhead has been widely recognized as a requirement for achieving efficient mappings which substantially reduce the execution time of parallel algorithms. This paper presents an iterative heuristic for static mapping of parallel algorithms to architectures. Special attention is given to measuring and reducing channel contention. Experimental results are used to show the effects of channel contention for packet-switched networks and the improvement realized by the authors' heuristic. They also present preliminary results for wormhole-routed networks.< >

关键词： parallel algorithms Concurrent computing parallel architectures Computer architecture Runtime Network topology Information science Computational Intelligence Society Processor scheduling Computational modeling

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Project Triton: towards improved programmability of parallel machines

Project Triton: towards improved programmability of parallel...

引用

Annual Hawaii international Conference on System Sciences (HICSS)

作者： M. Philippsen T.M. Warschko W.F. Tichy C.G. Herter Department of Informatics University of Karlsruhe Karlsruhe Germany

The approach taken in the Triton project is to let a high-level machine-independent parallel programming language drive the design of parallel hardware. This approach permits machine-independent parallel programs to be compiled into efficient machine code. The main results are as follows: (1) The parallel programming language Modula-2* extends Modula-2 with constructs for expressing a wide range of parallel algorithms in a high-level, portable, and readable way. (2) Techniques are used for efficiently translating Modula-2* programs to several modern parallel architectures and deriving recommendations for future parallel machine architectures. (3) Triton/1 is a scalable, mixed-mode SIMD/MIMD parallel computer with a highly efficient communications network. It overcomes several deficiencies of current parallel hardware and adequately supports high-level parallel languages.< >

关键词： parallel machines parallel programming Hardware parallel algorithms parallel architectures Computer architecture Computer networks Concurrent computing Portable computers Communication networks

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16th IFIP Working Group 7.3 international symposium on Computer Performance Modeling, Measurement and Evaluation and ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, 1993

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16th IFIP Working Group 7.3 international symposium on Computer Performance Modeling, Measurement and Evaluation and ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, 1993

ISBN: (纸本)9783540572978

The proceedings contain 26 papers. The special focus in this conference is on Computer Performance Modeling, Measurement and Evaluation. The topics include: parallel simulation;properties and analysis of queueing network models with finite capacities;performance analysis and optimization with the power-series algorithm;multiprocessor and distributed system design;response time distributions in queueing network models;fast simulation of rare events in queueing and reliability models;an inlxoduction to modeling dynamic behavior with time series analysis;issues in trace-driven simulation;maximum entropy analysis of queueing network models;performance modeling using DSPN express;relaxation for massively parallel discrete event simulation;an overview of tes processes and modeling methodology;performance engineering of client-server systems;queueing networks with finite capacities;performance instrumentation techniques for parallel systems;a survey of bottleneck analysis in closed networks of queues;software performance engineering;performance measurement using system monitors;providing quality of service packet switched networks;dependability and performability analysis;architectures and algorithms for digital multimedia on-demand servers;analysis and control of polling systems;modeling and analysis of transaction processing systems.

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