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检索条件"任意字段=International Symposium on Parallel Architectures, Algorithms, and Programming"

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A tensor product formulation of Strassen's matrix multiplication algorithm with memory reduction

A tensor product formulation of Strassen's matrix multiplica...

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international symposium on parallel Processing

作者： B. Kumar C.-H. Huang R.W. Johnson P. Sadayappan Departmentof Computer and Information Science Ohio State Uinversity Columbus OH USA Departmentof Computer Science Cloud State University Saint Cloud MN USA

A programming methodology based on tensor products has been used for designing and implementing block recursive algorithms for parallel and vector multiprocessors. A previous tensor product formulation of Strassen's matrix multiplication algorithm requires working arrays of size O(7/sup n/) for multiplying 2/sup n/*2/sup n/ matrices. The authors present a modified tensor product formulation of Strassen's algorithm in which the size of working arrays can be reduced to O(4/sup n/). The modified formulation exhibits sufficient parallel and vector operations for efficient implementation. Performance results on the Cray Y-MP are presented.< >

关键词： Tensile stress parallel programming Computerized monitoring NIST Algorithm design and analysis Vectors Linear algebra parallel machines Cloud computing Information science

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Total exchange on a reconfigurable parallel architecture

Total exchange on a reconfigurable parallel architecture

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Y.-D. Lyuu E. Schenfeld NEC Research Institute Inc. Princeton NJ USA

Total exchange is the densest parallel communication primitive and poses a severe test for the capability of any parallel architecture. This operation is very important and arises in many applications. We show that a reconfigurable parallel architecture called MICA can perform total exchange efficiently with simple algorithms. The mechanisms and structures of the reconfigurable switches, supporting simple total exchange algorithms, are presented. We introduce the basic operations the network supports as they are issued by the host to efficiently manage the network reconfiguration. Applications in linear algebra are briefly mentioned showing the way they can benefit from our architecture.< >

关键词： parallel architectures Network topology Switches Communication switching Testing Concurrent computing Computational efficiency National electric code Computer network management Application software

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PARSA: A parallel Program Scheduling and Assessment Environment

PARSA: A Parallel Program Scheduling and Assessment Environm...

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international Conference on parallel Processing (ICPP)

作者： Behrooz Shirazi Krishna Kavi A.R. Hurson Prasenjit Biswas Department of Computer Science & Engineering University of Texas Arlington Arlington TX USA Department of Electrical and Computer Engineering Pennsylvania State University University Park PA USA Cyrix Corporation Richardson TX USA

Efficient partitioning and scheduling of parallel programs and the distribution of data among pmessing elements are very important issues in parallel and distributed systems. Existing tools fdl short in addressing the issues satisfactorily. On one hand, it is believed to k unreasonable to leave the burden of these complex tasks to the programmers. On the other hand, fully automated schedulers have ken shown to be d little practical significance, or suitable only for restricted cases. In this paper we address the issues and algorithms for efficient partitioning and scheduling d parallel programs, including the distribution of data, in dislributed-memory multiprocessor systems, using the PARSA parallel software development environment. PARSA consists of a set of visual, interactive, compiletime tools that will provide automated program partitions and schedules whenever possible, while permitting the user to exert conml over these operations for a htter performance. The support program assessment tool provides the users the opportunity b fine-tune the program and achieve their performance objectives.

关键词： Processor scheduling Delay estimation programming profession Multiprocessing systems Partitioning algorithms Scheduling algorithm parallel architectures Delay effects parallel processing parallel programming

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A low-latency programming interface and a prototype switch for scalable high-performance distributed computing

A low-latency programming interface and a prototype switch f...

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international symposium on High Performance Distributed Computing

作者： T. Chen J. Feeney G. Fox G. Frieder S. Ranka B. Wilhelm F. Yu Northeast Parallel Architectures Center Syracuse University USA IBM NY USA School of Engineering and Applied Science George Washington University DC USA

This paper discusses the architecture and performance of a prototype switch for interconnecting IBM RISC System/6000 workstations. The paper describes the interconnection architecture and performance on a cluster of four IBM RISC System 6000 model 340 workstations. It also describes the driver level software interface to the switch and the features incorporated to minimize communication overhead. The performance measurements cover communication latency and bandwidth. In addition, performance measurements of Express, a popular parallel-programming interface, are provided.< >

关键词： Switches Prototypes Software prototyping Computer architecture Communication switching Reduced instruction set computing Workstations Measurement Delay Bandwidth

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Process Groups: a mechanism for the coordination of and communication among processes in the Venus collective communication library

Process Groups: a mechanism for the coordination of and comm...

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international symposium on parallel Processing

作者： V. Bala S. Kipnis Computer Sciences Department IBM Thomas J. Watson Research Center Yorktown Heights NY USA

In programming massively parallel computers, it is often necessary to have sets of processes cooperate in performing certain computations and communications. Most run-time libraries require that such sets of processes be explicitly specified in the program. In the Venus run-time communication library however, a Process Group abstraction is used to enable implicit coordination of and communication over dynamically determined sets of processes. The Process Groups mechanism in Venus offers an object-oriented approach for handling sets of processes and enhances the debugging and monitoring of programs. The authors describe the Process Groups mechanism in Venus, illustrate its use on the class of N-body problems, and outline some of the data structures and algorithms used to implement this mechanism in Venus.< >

关键词： Venus Concurrent computing Runtime library parallel programming Distributed computing Monitoring Application software Debugging Data structures Buildings

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An analysis of distributed computing software and hardware for applications in computational physics

An analysis of distributed computing software and hardware f...

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international symposium on High Performance Distributed Computing

作者： P.D. Coddington Northeast Parallel Architectures Center Syracuse University Syracuse NY USA

The author has implemented a set of computational physics codes on a network of IBM RS/6000 workstations used as a distributed parallel computer. He compares the performance of the codes on this network, using both standard Ethernet connections and a fast prototype switch, and also on the nCUBE/2, a MIMD parallel computer. The algorithms used range from simple, local, and regular to complex, non-local, and irregular. He describes his experiences with the hardware, software and parallel languages used, and discusses ideas for making distributed parallel computing on workstation networks more easily usable for computational physicists.< >

关键词： Distributed computing Hardware Computer networks Concurrent computing Physics computing Workstations Switches Code standards Ethernet networks Software prototyping

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A parallel computation network for the maximum clique problem

A parallel computation network for the maximum clique proble...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： F. Lin Software Engineering Laboratory Computer Engineering Department Santa Clara University Santa Clara CA USA

ISBN: (纸本)0780312813

The maximum clique problem is to find the maximum complete subgraph of a given graph G. A computation model for large-scale maximum clique problems is proposed and was tested. A parallel algorithm based on the maximum neural network which resembles the winner-takes-all circuit is introduced which solves large-scale problems in reasonable computation time that the best known algorithms cannot solve. The maximum clique problem is first formulated as an unconstrained quadratic zero-one programming problem and is solved by minimizing the weight summation over the same partition in a newly constructed graph.< >

关键词： Computer networks Concurrent computing Circuits Quadratic programming Neural networks Artificial neural networks Large-scale systems Very large scale integration Programmable logic arrays Compaction

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Data partitioning schemes for the parallel implementation of the revised simplex algorithm for LP problems

Data partitioning schemes for the parallel implementation of...

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international symposium on parallel Processing

作者： U. Sridhar A. Basu Center for Development of Advanced Computing Bangalore India

The parallel implementation of the revised simplex algorithm (RSA) using eta-factorization holds the promise of significant improvement in the execution time by virtue of the existence of a high degree of parallelism in the computation within an iteration of the algorithm. However, the scheme employed to partition key data structures in a distributed memory parallel processor has a great impact on the achievable performance. The paper explores the trade-offs between block-row and block-column partitioning schemes for the matrix of constraint coefficients vis-a-vis the communication overheads and granularity of parallel computations. The results of an approximate analysis of the compute-communication balance are compared with measurements from practical implementation of the partitioning schemes on C-DAC's PARAM 8000 distributed memory parallel processor.< >

关键词： Partitioning algorithms Concurrent computing Costs Data structures Distributed computing Memory management Linear programming Engineering management parallel processing Acceleration

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C parallelizing compiler on local-network-based computer environment

C parallelizing compiler on local-network-based computer env...

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international symposium on parallel Processing

作者： K. Asakura T. Watanabe N. Sugie Department of Information Engineering School of Engineering University of Nagoya Nagoya Japan

The local-network-based computer system, in which some workstations are connected is coming into practical use. Software development is, however, very difficult for end-users because the system has complicated problems such as load balancing, communication among processes on different workstations and so on. The authors propose a C-specific parallelizing compiler to solve these problems. The compiler adopts function call parallelization, and takes less communication overhead than DO loop parallelization.< >

关键词： Concurrent computing Program processors Workstations Distributed computing Distributed processing Computer networks Partitioning algorithms Costs programming Load management

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parallel network dual simplex method on a shared memory multiprocessor

Parallel network dual simplex method on a shared memory mult...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： K. Thulasiraman R.P. Chalasani M.A. Comeau Concordia University Montreal Canada

We present a parallel algorithm for solving the dual transshipment problem. The traditional dual simplex method does not offer much scope for parallelization, because it moves from one basic feasible solution to another, performing one pivot operation at a time. We present a new method called modified network dual simplex method which uses concurrent pivots. This departure from the traditional LP approach raises several issues such as the need to convert a non-basic feasible solution to a basic feasible solution. We present our strategies to handle these issues as well as the corresponding parallel algorithms. We also present results of testing this algorithm on large graphs to solve the integrated layout compaction and wire balancing problem.< >

关键词： parallel algorithms Wire Very large scale integration Compaction Joining processes Testing Tree graphs Linear programming Relaxation methods Design methodology

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