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Simulation of SIMD and MIMD shared memory architectures on Unix-based systems

Simulation of SIMD and MIMD shared memory architectures on U...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： L. Sousa M. Piedade Faculty de Ciências e Tecnologia UNL Monte de Caparica Portugal Electrical Engineering Department IST Lisboa Portugal

A set of tools to simulate SIMD (single instruction multiple data) and MIMD (multiple instruction multiple data) shared memory architectures on multitasking sequential systems is presented. The main objective of these tools is to evaluate parallel computing systems. As is well known, the performance of the parallel algorithms, unlike that of serial algorithms, is very machine dependent. The simulation is based on an algorithm-driven approach, allowing the test and evaluation of algorithms for this type of architecture. The evaluation of the algorithms is done at run-time, making possible the acquisition of very realistic results. Different levels of evaluation can be applied. More accurate results are achieved at the expense of more simulation time. Simulation tools have been developed in C language for Unix based systems, assuring portability among a large class of computing systems. The tools presented have been extensively used to simulate orthogonal multiprocessing systems, especially for the development and simulation of several image processing algorithms. Experimental results show that a good approach to the real system operation has been achieved.< >

关键词： Memory architecture Computational modeling Multitasking parallel processing parallel algorithms Testing Computer architecture Runtime Multiprocessing systems Image processing

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A parallel approach to hybrid range image segmentation

A parallel approach to hybrid range image segmentation

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international symposium on parallel Processing

作者： N. Giolmas D.W. Watson D.M. Chelberg H.J. Siegel Parallel Processing Laboratory School of Electrical Engineering Purdue University West Lafayette IN USA Sch. of Electr. Eng. Purdue Univ. West Lafayette IN USA

parallel processing methods are an attractive means to achieve significant speedup of computationally expensive image understanding algorithms, such as those applied to range images. Mixed-mode parallel systems are ideally suited to this area because of the flexibility in using the different modes of parallelism. The trade-offs of using different parallel modes are examined through the implementation of hybrid range segmentation operations, characteristic of a broad class of low level image processing algorithms. Alternative means of distributing data among the processing elements that achieve improved performance are considered. Results comparing different implementations on a single reconfigurable parallel processor. PASM, indicate some generally applicable guidelines for the effective parallelization of vision algorithms.< >

关键词： Image segmentation parallel processing parallel architectures Pixel Sea surface Partitioning algorithms Image processing Image edge detection Concurrent computing Switches

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The concepts of COMPAR- a compiler for massively parallel architectures

The concepts of COMPAR- a compiler for massively parallel ar...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： U. Arzt J. Teich L. Thiele Institute of Microelectronics University of Saarland Saarbruecken Germany

Describes the concepts of a compiler for mapping programs onto massively parallel architectures, e.g. VLSI signal processing arrays, and general-purpose-type massively parallel architectures, e.g. digital signal processors. The input to the system is a single-assignment code. Using a transformative approach, the initial program is refined using provably correct program transformations in order to solve typical mapping problems. These are the localization of global data dependencies, the scheduling of computations in time and space, the generation of control, and the matching of resource constraints. After application of the architecture-independent transformation tools, a back end consisting of architecture-dependent generators creates output code from the transformed program. Thus, architecture-independent design of parallel programs is possible. The main concepts of the COMPAR design system are described. The software instances of the implementation are modeled, and the class of input programs is formally introduced. The design flow is explained by introducing the required program transformations. The main advantages of the system in comparison to similar design systems are outlined.< >

关键词： parallel architectures Signal processing algorithms Program processors Very large scale integration Aerospace electronics Computer architecture Algorithm design and analysis parallel processing Array signal processing Pipeline processing

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Formal derivation of an efficient parallel 2-D Gauss-Seidel method

Formal derivation of an efficient parallel 2-D Gauss-Seidel ...

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international symposium on parallel Processing

作者： J.A. Yang Y.-I. Choo Department of Computer Science Yale University New Heaven CT USA

Presents a formal derivation of a highly efficient parallel implementation of the 2-D Gauss-Seidel method for machines based on the two-dimensional mesh of processors. A methodology is illustrated which formalizes the process of mapping and scheduling a high level algorithm onto a particular target parallel architecture. It starts from a simple initial program. Equational transformations are then applied: to partition the abstract problem onto processors; to make communication among processors explicit; to pipeline the computation by wave-front scheduling; and finally to map logical processors onto physical processors for perfect processor utilization. All the derivation steps preserve equalities so that the derived programs are equivalent to the initial program. Using this methodology, the paper develops efficient implementations for other parallel architectures.< >

关键词： Gaussian processes Processor scheduling parallel architectures Two dimensional displays Scheduling algorithm Filters Computer science Partitioning algorithms Equations Pipelines

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Visual debugging for a pyramidal machine

Visual debugging for a pyramidal machine

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international Conference on Pattern Recognition

作者： A. Biancardi M. Mosconi Dipartimento di Informatica e Sistemistica University of Pavia Italy

This paper proposes a novel approach to program development for highly parallel architectures, primarily as far as debugging is concerned. The visual nature of the debugging stage, when dealing with image-processing algorithms, is heavily supported so that all the relevant information, which is generally either hidden or presented without its logical structures, is made available to programmers. The authors present the modular and portable software system built, in Pavia University, for the PAPIA2 machine.< >

关键词： Debugging programming profession parallel architectures System testing Costs Application software parallel processing Image processing Concurrent computing Computational modeling

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No pain and gain!-experiences withMentat on a biological application

No pain and gain!-experiences withMentat on a biological app...

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international symposium on High Performance Distributed Computing

作者： A.S. Grimshaw E.A. West W.R. Pearson Department of Computer Science University of Virginia USA Department of Biochemistry University of Virginia USA

Throughout much of the parallel processing community there is the sense that writing software for distributed memory parallel processors is subject to a 'no pain-no gain' rule: that in order to reap the benefits of parallel computation one must first suffer the pain of converting the application to run on a parallel machine. The authors believe this is the result of inadequate programming tools and not a problem inherent to parallel processing. They show that one can parallelize real scientific applications and obtain good performance with little effort if the right tools are used. Their vehicle for this demonstration is a six-thousand line DNA and protein sequence comparison application that they have implemented in Mentat, an object-oriented parallel processing system for both parallel and distributed architectures. They briefly describe the application and present performance information for both the Mentat version and a hand-coded parallel version of the application.< >

关键词： Pain parallel processing Writing Biology computing Concurrent computing Distributed computing Application software parallel machines parallel programming Vehicles

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parallel MD recursive digital filtering using 1D vector recursive filters

Parallel MD recursive digital filtering using 1D vector recu...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： X. Lui L.T. Bruton Dept. of Electr. Eng. Calgary Univ. Alta. Canada Department of Electrical Engineering University of Calgary Calgary AB Canada

It is shown that a parallel MD (multidimensional) recursive digital filter algorithm can be derived from a given sequential MD recursive filter algorithm, where no additional arithmetic operations occur if appropriate recursion directions are used for processing MD data. The derived parallel filter is expressible as a 1-D vector system whose coefficient matrices are directly related to the coefficients of the original sequential system. The stability of this 1-D vector system leads to the result that the original sequential system possesses the practical BIBO (bounded input, bounded output) property.< >

关键词： Digital filters Difference equations parallel processing Filtering algorithms Stability Multidimensional systems Throughput Hardware parallel architectures parallel algorithms

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parallel implementation of divide-and-conquer algorithms on binary de Bruijn networks

Parallel implementation of divide-and-conquer algorithms on ...

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international symposium on parallel Processing

作者： Xiaoxiong Zhong S. Rajopadhye V.M. Lo Department of CS. University of Oregon USA Department of ECE Oregon State University USA

Studies the problem of parallel implementation of divide-and-conquer algorithms on binary de Bruijn network using a temporal binomial tree (rather than the usual binary tree) computation structure. Two cases of message volumes are considered: (i) uniform, and (ii) logarithmically decreasing (increasing) weights. A single mapping is proposed for both cases. It has average extra dilation 1 and is communication link contention-free. A lower bound for the total extra dilation of any mapping from uniform-weighted binomial tree to an arbitrary degree-4 network is also developed to show that the mapping is asymptotically optimal with respective to the average extra dilation. The implementation is well suited to a binary de Bruijn network with a wormhole or circuit switching communication scheme.< >

关键词： Binary trees Computer networks Concurrent computing Switching circuits parallel architectures Hypercubes Prototypes Decoding Propulsion Joining processes

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Single processor-pool MSIMD/MIMD architectures

Single processor-pool MSIMD/MIMD architectures

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international symposium on parallel and Distributed Processing (IPDPS)

作者： M.S. Baig T.A. El-Ghazawi N.A. Alexandridis Department of Electrical Engineering and Computer Science George Washington University DC USA

In multiple SIMD/MIMD (single-instruction multiple-data/multiple-instruction multiple-data) (MSIMD/MIMD) architectures, two different types of processors are used: processing elements (PEs), to support both SIMD and MIMD partitions, and control units (CUs), to support SIMD partitions. In the existing architectures, the role of a processor to run as either PE or CU is determined only at design time. It is shown that this fixed assignment results in performance degradations. Furthermore, a single processor-pool MSIMD/MIMD architectural model with dynamic processor assignments is introduced. A cube-based single processor-pool system is presented. This system is referred to as the single-pool processor (SPP). Simulation and analysis have shown that the proposed SPP architecture offers a significantly better performance/cost than other MSIMD/MIMD systems.< >

关键词： Computer architecture Degradation Analytical models Performance analysis Supercomputers programming profession Runtime Application software Acceleration Process design

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A parallel algorithm for recognizing the shuffle of two strings

A parallel algorithm for recognizing the shuffle of two stri...

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international symposium on parallel Processing

作者： A. Saoudi M. Nivat C.P. Rangan R. Sundaram G.D.S. Ramkumar L.I.P.N. Institut Galilée Universite Paris XIII Villetaneuse France L.I.T.P. Universite Paris VII Paris France Department of Computer Science and Engineering Indian Insitute of Technology Chennai India

Presents a parallel algorithm for verifying that a string X is formed by the shuffle of two strings Y and Z. The algorithm runs in O(log/sup 2/n) time with O(n/sup 2//log/sup 2/n) processors on the EREW-PRAM model.

关键词： parallel algorithms Polynomials Dynamic programming Transmission line matrix methods

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