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parallel Implementation Strategies for Hierarchical Non-uniform Memory Access Systems by Example of the Scale-Invariant Feature Transform Algorithm

Parallel Implementation Strategies for Hierarchical Non-unif...

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IEEE international symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Max Plauth Wieland Hagen Frank Feinbube Felix Eberhardt Lena Feinbube Andreas Polze Operating Systems and Middleware Group University of Potsdam Germany

ISBN: (纸本)9781509036837

The domains of parallel and distributed computing have been converging continuously up to the degree that state-of-the-art server computer systems incorporate characteristics from both domains: They comprise a hierarchy of enclosures, where each enclosure houses multiple processor sockets and each socket again contains multiple memory controllers. A global address space and cache coherency are facilitated using multiple layers of fast interconnection technologies even across enclosures. The growing popularity of such systems creates an urge for efficient mappings of cardinal algorithms onto such hierarchical architectures. However, the growing complexity of such systems and the inconsistencies between implementation strategies of different hardware vendors make it increasingly harder to do find efficient mapping strategies that are universally valid. In this paper, we present scalable optimization and mapping strategies in a case study of the popular Scale-Invariant Feature Transform (SIFT) computer vision algorithm. Our approaches are evaluated using a state-of-the-art hierarchical Non-Uniform Memory Access (NUMA) system with 240 physical cores and 12 terabytes of memory, apportioned across 16 NUMA nodes (sockets). SIFT is particularly interesting since the algorithm utilizes a variety of common data access patterns, thus allowing us to discuss the scaling properties of optimization strategies from the distributed and parallel computing domains and their applicability on emerging server systems.

关键词： Hardware Optimization Sockets Graphics processing units Dogs Feature extraction Servers

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Performance evaluation of real time schedulers for a multicomputer

Performance evaluation of real time schedulers for a multico...

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international Workshop/symposium on Distributed Simulation and Real-Time Applications (DS-RT)

作者： R.L. Cancian L.F. Friedrich Computer Science Department Vale do Itajaí University Itajuba Santa Catarina Brazil CPGCC Santa Catarina Federal University Universidade Federal de Santa Catarina Florianopolis Brazil

This paper considers work in the context of the CRUX project, which aims at the conception of a complete environment for parallel programming, in the development of a postgraduate course in Computer Science of Santa Catarina Federal University. This paper discusses a performance evaluation of several scheduling algorithms of real time systems found in the bibliography, about a simulation model that represents the processing as the communication of this multicomputer. The objective was to quantify the effect of the scheduling algorithm and other factors about some metrics of selected performance, in order to verify the applicability of CRUX in real time systems.

关键词： Processor scheduling Real time systems Scheduling algorithm Network topology Multiprocessor interconnection networks Computer science Bibliographies Control systems Time measurement parallel programming

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Graphite: A distributed parallel simulator for multicores

Graphite: A distributed parallel simulator for multicores

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IEEE symposium on High-Performance Computer Architecture

作者： Jason E. Miller Harshad Kasture George Kurian Charles Gruenwald Nathan Beckmann Christopher Celio Jonathan Eastep Anant Agarwal Massachusetts Institute of Technology Cambridge MA USA

This paper introduces the Graphite open-source distributed parallel multicore simulator infrastructure. Graphite is designed from the ground up for exploration of future multi-core processors containing dozens, hundreds, or even thousands of cores. It provides high performance for fast design space exploration and software development. Several techniques are used to achieve this including: direct execution, seamless multicore and multi-machine distribution, and lax synchronization. Graphite is capable of accelerating simulations by distributing them across multiple commodity Linux machines. When using multiple machines, it provides the illusion of a single process with a single, shared address space, allowing it to run off-the-shelf pthread applications with no source code modification. Our results demonstrate that Graphite can simulate target architectures containing over 1000 cores on ten 8-core servers. Performance scales well as more machines are added with near linear speedup in many cases. Simulation slowdown is as low as 41× versus native execution.

关键词： Multicore processing Computational modeling Computer architecture programming Open source software Application software Hardware Acceleration Linux Performance evaluation

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A VLSI architecture for the implementation of real-time order statistic filters

A VLSI architecture for the implementation of real-time orde...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： N.R. Murthy M.N.S. Swamy Concordia University Montreal Canada

The authors give an algorithm for the real-time computation of the running order statistic (ROS). Order statistic filters (OSFs) or ranked order filters (ROFs) are a class of nonlinear digital filters which have found applications in image processing and in smoothing of speech data. Real-time implementation of an OSF requires the computation of the order statistic (ranked order) of the samples in a window (usually containing an odd number of samples) which gets periodically updated with the arrival of a new sample(s). A modular and highly parallel architecture characterized by programmable window size and required rank order is proposed for the implementation of the algorithm in VLSI form.< >

关键词： Very large scale integration Statistics Image processing Digital filters parallel architectures Signal processing Software algorithms Smoothing methods Speech processing Sorting

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QbDJ: A Novel Framework for Handling Skew in parallel Join Processing on Distributed Memory

QbDJ: A Novel Framework for Handling Skew in Parallel Join P...

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IEEE international Conference on High Performance Computing and Communications (HPCC)

作者： Long Cheng Spyros Kotoulas Tomas E. Ward Georgios Theodoropoulos National University of Ireland Maynooth Ireland IBM Res. Dublin Ireland Durham University UK

The performance of parallel distributed data management systems becomes increasingly important with the rise of Big Data. parallel joins have been widely studied both in the parallel processing and the database communities. Nevertheless, most of the algorithms so far developed do not consider the data skew, which naturally exists in various applications. State of the art methods designed to handle this problem are based on extensions to either of the two prevalent conventional approaches to parallel joins - the hash-based and duplication-based frameworks. In this paper, we introduce a novel parallel join framework, query-based distributed join (QbDJ), for handling data skew on distributed architectures. Further, we present an efficient implementation of the method based on the asynchronous partitioned global address space (APGAS) parallel programming model. We evaluate the performance of our approach on a cluster of 192 cores (16 nodes) and datasets of 1 billion tuples with different skews. The results show that the method is scalable, and also runs faster with less network communication compared to state-of-art PRPD approach in [1] under high data skew.

关键词： Arrays Distributed databases Histograms parallel processing Instruction sets Probes Silicon

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A divide and conquer approach to shortest paths in planar layered digraphs

A divide and conquer approach to shortest paths in planar la...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： S. Sairam R. Tamassia J.S. Vitter Department of Computer Science Brown University Providence RI USA

The authors give efficient parallel algorithms to compute shortest-paths in planar layered digraphs. They show that these digraphs admit special kinds of separators, called one-way separators, which allow paths in the graph to cross them only once. They use these separators to give divide-and-conquer solutions to the problem of finding the shortest paths. They first give a simple algorithm that works on the CREW (concurrent-read exclusive-write) PRAM (parallel random-across machine) model and computes the shortest path between any two vertices of an n-node planar layered diagraph in time O(log/sup 3/ n) using n/log n processors. A CRCW (concurrent-read concurrent-write) version of this algorithm runs in O(log/sup 2/ n log log n) time and uses O(n/log log n) processors. The authors then improve the time bound to O(log/sup 2/ n) on the CREW model and O(log n log log n) on the CRCW model. The processor bounds still remain n log n for the CREW model and n/log log n for the CRCW model.< >

关键词： Computer science parallel algorithms Concurrent computing Particle separators Shortest path problem Sparse matrices Transmission line matrix methods Phase change random access memory Application software Dynamic programming

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Automatic Insertion of Copy Annotation in Data-parallel Programs

Automatic Insertion of Copy Annotation in Data-Parallel Prog...

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international symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

作者： Gleison Souza Diniz Mendonça Breno Campos Ferreira Guimarães Péricles Rafael Oliveira Alves Fernando Magno Quintão Pereira Márcio Machado Pereira Guido Araújo Universidade Federal de Minas Gerais Belo Horizonte MG BR Unicamp Campinas Brazil

Directive-based programming models, such as OpenACC and OpenMP arise today as promising techniques to support the development of parallel applications. These systems allow developers to convert a sequential program into a parallel one with minimum human intervention. However, inserting pragmas into production code is a difficult and error-prone task, often requiring familiarity with the target program. This difficulty restricts the ability of developers to annotate code that they have not written themselves. This paper provides one fundamental component in the solution of this problem. We introduce a static program analysis that infers the bounds of memory regions referenced in source code. Such bounds allow us to automatically insert data-transfer primitives, which are needed when the parallelized code is meant to be executed in an accelerator device, such as a GPU. To validate our ideas, we have applied them onto Polybench, using two different architectures: Nvidia and Qualcomm-based. We have successfully analyzed 98% of all the memory accesses in Polybench. This result has enabled us to insert automatic annotations into those benchmarks leading to speedups of over 100x.

关键词： Open area test sites Graphics processing units Kernel Arrays Standards Syntactics

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Fast Radix Sort for Sparse Linear Algebra on GPU 14

Fast Radix Sort for Sparse Linear Algebra on GPU

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Simulation Multi-Conference

作者： Lukas Polok Viorela Ila Pavel Smrz Brno University of Technology Bozetechova Czech Republic

ISBN: (纸本)9781632662163

Fast sorting is an important step in many parallel algorithms, which require data ranking, ordering or partitioning. parallel sorting is a widely researched subject, and many algorithms were developed in the past. In this paper, the focus is on implementing highly efficient sorting routines for the sparse linear algebra operations, such as parallel sparse matrix - matrix multiplication, or factorization. We propose a fast and simple to implement variant of parallel radix sort algorithm, suitable for GPU architecture. Extensive testing on both synthetic and real-world data shows, that our method outperforms other similar state-of-the-art implementations. Our implementation is bandwidth-efficient, as it achieves sorting rates comparable to the theoretical upper bound of memory bandwidth. We also present several interesting code optimizations relevant to GPU programming.

关键词： parallel sorting Radix sort Sparse matrix Matrix-matrix multiplication

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A programming model for reconfigurable computing based in functional concurrency

A programming model for reconfigurable computing based in fu...

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international Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

作者： William L. Harrison Ian Graves Adam Procter Michela Becchi Gerard Allwein Department of Computer Science University of Missouri Department of Electrical & Computer Engineering University of Missouri US Naval Research Laboratory Washington DC

ISBN: (纸本)9781509025213

FPGA programmability remains a concern with respect to the broad adoption of the technology. One reason for this is simple: FPGA applications are frequently implementations of concurrent algorithms that could be most directly rendered in concurrent languages, but there is little or no first-class support for concurrent applications in conventional hardware description languages. It stands to reason that FPGA programmability would be enhanced in a hardware description language with first-class concurrency. The starting point for this paper is a functional hardware description language with built-in support for concurrency called ReWire. Because it is a concurrent functional language, ReWire supports the elegant expression of common concurrency paradigms; we illustrate this with several case studies.

关键词： Hardware Concurrent computing Clocks parallel processing programming Software engineering Computational modeling

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international journal of emerging technologies in computational and Applied Sciences (IJETCAS) A Comparative study of association rule mining algorithms on Grid and Cloud Platform

arXiv

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arXiv 2017年

作者： Singh, Sudhakar Garg, Rakhi Mishra, P.K. Department of Computer Science - Faculty of Science 13 Singapore Mahila Maha Vidyalaya2 Banaras Hindu University 123 India Varanasi UP221005 India

Association rule mining is a time consuming process due to involving both data intensive and computation intensive nature. In order to mine large volume of data and to enhance the scalability and performance of existing sequential association rule mining algorithms, parallel and distributed algorithms are developed. These traditional parallel and distributed algorithms are based on homogeneous platform and are not lucrative for heterogeneous platform such as grid and cloud. This requires design of new algorithms which address the issues of good data set partition and distribution, load balancing strategy, optimization of communication and synchronization technique among processors in such heterogeneous system. Grid and cloud are the emerging platform for distributed data processing and various association rule mining algorithms have been proposed on such platforms. This survey article integrates the brief architectural aspect of distributed system, various recent approaches of grid based and cloud based association rule mining algorithms with comparative perception. We differentiate between approaches of association rule mining algorithms developed on these architectures on the basis of data locality, programming paradigm, fault tolerance, communication cost, partition and distribution of data sets. Although it is not complete in order to cover all algorithms, yet it can be very useful for the new researchers working in the direction of distributed association rule mining algorithms. Copyright © 2017, The Authors. All rights reserved.

关键词： MapReduce

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