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A decision support system for the algorithm-architecture mapping problem

A decision support system for the algorithm-architecture map...

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IEEE international Conference on Systems, Man and Cybernetics

作者： K.R. Pattipati R.T. Lee S.A. Shah P.B. Luh Department of Electrical and System Engineering University of Connecticut Storrs CT USA

This paper presents a decision support system, termed MAPPER, for the mapping of large scale resource allocation algorithms onto parallel computing architectures. The mapping problem is viewed as one of assigning the nodes of a finite, directed, acyclic task graph (representing the logical and data dependencies among the tasks constituting the algorithm) onto the nodes of a finite, undirected processor graph (denoting the parallel computing architecture). The objective is to minimize the completion time of the algorithm such that the redundancy, processor memory, and security constraints are satisfied. Key features of MAPPER are its graphical user interface, an explicit model of task and message queueing, and the incorporation of precedence relationships among the tasks of the algorithm. Four mapping algorithms are embedded in MAPPER. The first algorithm is a two-stage heuristic that determines the order of task execution based on the critical path method(CPM), and then employs a one-step optimization method to determine the task allocation. The second algorithm employs the idea of pair-wise exchange on task execution order to improve the performance of the heuristic algorithm. The third algorithm is an optimal mapping strategy using A* algorithm, wherein a lower bound on the cost-to-go is obtained from the two-stage heuristic. Finally, an /spl epsiv/-optimal algorithm, A*/sub /spl epsiv//, is developed to subdue the combinatorial explosion of the A* algorithm.

关键词： Decision support systems Partitioning algorithms Resource management Large-scale systems parallel processing Linear programming Systems engineering and theory Computer architecture Graphical user interfaces Optimization methods

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CellMR: A framework for supporting mapreduce on asymmetric cell-based clusters

CellMR: A framework for supporting mapreduce on asymmetric c...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： M. Mustafa Rafique Benjamin Rose Ali R. Butt Dimitrios S. Nikolopoulos Department of Computer Science Virginia Technology Blacksburg VA USA Institute of Computer Science Foundation for Research and Technology Hellas Crete Greece

The use of asymmetric multi-core processors with on-chip computational accelerators is becoming common in a variety of environments ranging from scientific computing to enterprise applications. The focus of current research has been on making efficient use of individual systems, and porting applications to asymmetric processors. In this paper, we take the next step by investigating the use of multi-core-based systems, especially the popular Cell processor, in a cluster setting. We present CellMR, an efficient and scalable implementation of the MapReduce framework for asymmetric Cell-based clusters. The novelty of CellMR lies in its adoption of a streaming approach to supporting MapReduce, and its adaptive resource scheduling schemes: Instead of allocating workloads to the components once, CellMR slices the input into small work units and streams them to the asymmetric nodes for efficient processing. Moreover, CellMR removes I/O bottlenecks by design, using a number of techniques, such as double-buffering and asynchronous I/O, to maximize cluster performance. Our evaluation of CellMR using typical MapReduce applications shows that it achieves 50.5% better performance compared to the standard nonstreaming approach, introduces a very small overhead on the manager irrespective of application input size, scales almost linearly with increasing number of compute nodes (a speedup of 6.9 on average, when using eight nodes compared to a single node), and adapts effectively the parameters of its resource management policy between applications with varying computation density.

关键词： Acceleration Processor scheduling Distributed computing Multicore processing Resource management Computer architecture High performance computing parallel architectures Data processing parallel programming

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Breaking the Barriers: Two Models for MPI programming 98

Breaking the Barriers: Two Models for MPI Programming

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Proceedings of the 1998 international Conference on parallel architectures and Compilation Techniques

作者： Jose Luis Roda Casiano Rodriguez-Leon Daniel Gonzalez-Morales Francisco Almeida-Rodriguez Pablo Pulido Daniel Dorta

ISBN: (纸本)9780818685910

The asynchronous nature of many MPI/PVM programs does not fit the BSP model. The barrier synchronization imposed by the model restricts the range of available algorithms and their performance. Through the suppression of barriers and the generalization of the concept of superstep we propose two new models, the BSP-like and the BSP Without Barriers (BSPWB) models. While the BSP-like extends the BSP* model to programs written using collective operations, the more general BSPWB model admits the MPI/PVM parallel asynchronous programming style. As LogP, the model encourages locality but it is simpler to use. The parameters of the models and their quality are evaluated on a distributed-shared memory machine, the Origin 2000 and on a distributed memory machine, the CRAY T3E. The dependence of the time spent in an h-relation is stronger in the communication pattern than in the number of processors. The total variation of the h-relation time in both the patterns and processor numbers is smaller than sixty nanoseconds. To illustrate the proposed models, two different applications are considered: a parallel Sort using Regular Sampling (PSRS) and a parallel Dynamic programming Algorithm solving the Single Resource Allocation Problem (SRAP). The PSRS is a synchronous algorithm with a rich set of collective communication patterns and coarse grain communications. On the opposite extreme, the SRAP is a fine grain communication algorithm using permutation patterns. The computational results prove the accuracy of the models. The prediction of the communication times is robust even for the SRAP, where communication is dominated by small messages.

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An evaluation of DELTA, a decoupled pre-fetching virtual shared memory system

An evaluation of DELTA, a decoupled pre-fetching virtual sha...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： I. Watson A. Rawsthorne M. Cumpstey F. Charpin Department Computer Science University of Manchester Institute of Science and Technology Manchester UK

Decoupled pre-fetching is a technique for reducing the page miss overheads in Distributed Shared Memory systems by separating out those instructions responsible for data fetching from the main instruction stream and running them on a separate CPU whose function is to predict store accesses ahead of time. This approach differs from other pre-fetching approaches in that the predictions of data usage are obtained dynamically from partial evaluation of the program and this promises to produce considerably better performance in circumstances where the access patterns are non-regular and cannot be extracted by static analysis of the program. This paper reviews the techniques of decoupled pre-fetching with particular emphasis on Cache only Memory architectures (COMA). It then presents a more thorough evaluation of the ideas than has previously been attempted using some of the SPLASH benchmarks. It is shown that the techniques perform well on some programs but that, as expected, the benefits of pre-fetching are negated when there is a high rate of data invalidation caused by global updating.

关键词： Memory architecture Yarn Switches Computer science Data mining Distributed decision making Delay programming profession Program processors Data structures

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A segment-based DSM supporting large shared object space 06

A segment-based DSM supporting large shared object space

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international symposium on parallel and Distributed Processing (IPDPS)

作者： B.W.-L. Cheung Cho-Li Wang Department of Computer Science University of Hong Kong Hong Kong China

ISBN: (纸本)9781424400546

This paper introduces a software DSM that can extend its shared object space exceeding 4GB in a 32-bit commodity cluster environment. This is achieved through the dynamic memory mapping mechanism, with local hard disks as backing store. We introduce the new concept of segments with intelligent splitting to reduce network traffic, false sharing as well as adapt better to the shared memory access patterns. A priority-based swapping algorithm is designed to reduce disk accesses for efficient dynamic memory mapping, and maximize the use of disk space as shared object space. A new queue-based scheme is also devised for efficient and simple management of memory blocks. The proposed solutions were implemented in LOTS V.2, and it can outperform its previous version when running small applications, while the maximum shared object space is increased to one-third of the total free disk space available among all the nodes

关键词： Application software programming profession Clustering algorithms Random access memory Computer science Hard disks Intelligent networks Telecommunication traffic Traffic control Algorithm design and analysis

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Placement and routing of Boolean functions in constrained FPGAs using a distributed genetic algorithm and local search

Placement and routing of Boolean functions in constrained FP...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： M.R. del Solar J.M.S. Perez J.A.G. Pulido M.A.V. Rodriguez Department de Informática Escuela Politécnica Caceres Spain

In this work we present a system for implementing the placement and routing stages in the FPGA cycle of design, into the physical design stage. We start with the ISCAS benchmarks, on EDIF format, of Boolean functions to be implemented. They are processed by a parser in order to obtain an internal representation which is able to be processed by a genetic algorithm (GA) tool. This tool develops the placement and routing tasks, considering possible restricted area into the FPGA. In order to help to the GA to make the routing stage we have added a local search procedure. That local search gets a path between two points without considering neither their placement nor the restricted areas among them. The GA is fully customizable, featuring the ability to work with one or several islands. The experiments have verified that using distributing execution improves the costs and speeds up the convergence towards better results in smaller slots of time

关键词： Routing Boolean functions Field programmable gate arrays Genetic algorithms Wire Circuits Biological cells Genetic programming Design automation Libraries

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Non-iteration parallel Algorithm for Frequent Pattern Discovery

Non-iteration Parallel Algorithm for Frequent Pattern Discov...

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13th international symposium on Distributed Computing and Applications to Business,Engineering & Science（DCABES 2014）

作者： Chun Liu Yuqiang Li School of Computer Science and Technology Wuhan University of Technology

For the high time overhead problems of Apriori algorithm while solving for the long length frequent patterns, using the Map Reduce distributed programming ideas, the paper breaks the original idea of Aproiri which discovers the frequent item sets through gradually increasing the element numbers in the frequent item sets. It proposes a new non-iteration parallel algorithm about frequent pattern discovery, which can get arbitrary length frequent pattern at random. The experimental results show that the proposed algorithm has better time performance than such parallel algorithms which are under the ideas of traditional Apriori algorithm.

关键词： frequent pattern discovery parallel algorithm non-iteration Map Reduce

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Evaluation of Hybrid parallel Cell List algorithms For Monte Carlo Simulation

Evaluation of Hybrid Parallel Cell List Algorithms For Monte...

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IEEE international symposium on Cyberspace Safety and Security

作者： Kamel Rushaidat Loren Schwiebert Brock Jackman Jason Mick Jeffrey Potoff Department of Computer Science Wayne State University Department of Chemical Engineering and Materials Science Wayne State University

ISBN: (纸本)9781479989386

This paper describes efficient, scalable parallel implementations of the conventional cell list method and a modified cell list method to calculate the total system intermolecular Lennard-Jones force interactions in the Monte Carlo Gibbs ensemble. We targeted this part of the Gibbs ensemble for optimization because it is the most computationally demanding part of the force interactions in the simulation, as it involves all the molecules in the system. The modified cell list implementation reduces the number of particles that are outside the interaction range by making the cells smaller, thus reducing the number of unnecessary distance evaluations. Evaluation of the two cell list methods is done using a hybrid MPI+OpenMP approach and a hybrid MPI+CUDA approach. The cell list methods are evaluated on a small cluster of multicore CPUs, Intel Phi coprocessors, and GPUs. The performance results are evaluated using different combinations of MPI processes, threads, and problem sizes.

关键词： Cell List Monte Carlo Simulations Hybrid parallel architectures Gibbs Ensemble

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Experimental verification and benchmark of in-memory principal component analysis by crosspoint arrays of resistive switching memory

Experimental verification and benchmark of in-memory princip...

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IEEE international symposium on Circuits and Systems

作者： Piergiulio Mannocci Andrea Baroni Enrico Melacarne Cristian Zambelli Piero Olivo Eduardo Perez Christian Wenger Daniele Ielmini

ISBN: (数字)9781665484855

ISBN: (纸本)9781665484862

In-memory computing (IMC) is gaining momentum as the most promising candidate for the upcoming non-von-Neumann, machine learning-optimized computing paradigm. Its intrinsic parallelism is well-suited to accelerate matrix-vector multiplications (MVM), which prove challenging for traditional architectures and are a fundamental operation in principal component analysis (PCA), one of the most renowned algorithms for data classification. Here, we show an experimental demonstration of a novel, IMC-based PCA algorithm by in-memory power iteration and deflation executed in a 4-kbit array of resistive random-access memory (RRAM). Our algorithm achieves 95.25% classification accuracy on the Wisconsin Diagnostic Breast Cancer dataset, matching closely results of a floating-point machine while providing a 250 improvement in energy efficiency.

关键词： Semiconductor device modeling Machine learning algorithms Switches Computer architecture parallel processing In-memory computing Energy efficiency

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Implementation of an improved parallel code phase search algorithm for GPS signal acquisition on Zynq SoC

Implementation of an improved parallel code phase search alg...

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international symposium on Artificial Intelligence and Signal Processing (AISP)

作者： Amirreza Taghdiri Ali Moftakharzadeh Pouya Zahedi Hadi Safdarkhani dept. Electrical Engineering Yazd University Yazd Iran

In the field of Global Positioning System (GPS), signal acquisition stands as the initial and crucial step in the signal processing chain. Numerous algorithms have been proposed for acquisition, and this paper introduces enhancements to the parallel Code-phase Search (PCS) algorithm utilized for acquiring GPS satellite signals. Our approach involves the generation of carrier replica and PRN code, as well as the calculation of the FFT conjugate of the PRN code using MATLAB, with subsequent storage in an SD-Card. A key improvement lies in utilizing a single FFT IPCore for both FFT and IFFT computations, eliminating the need for two FFT IPCores and one IFFT IPCore as seen in the original PCS algorithm. This optimization results in reduced consumption of DSP blocks and memory resources. Furthermore, we compared different architectures, namely Radix-4, Radix-2, and Radix-2lite, in terms of clock cycles, resource utilization, and power consumption. The Radix-4 architecture was chosen due to its efficiency. This enhancement not only lowers power consumption by at least 8.8% but also increases the algorithm execution time while reducing overall costs.

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