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检索条件"任意字段=International Symposium on Parallel Architectures, Algorithms, and Programming"

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Placement and routing of Boolean functions in constrained FPGAs using a distributed genetic algorithm and local search

Placement and routing of Boolean functions in constrained FP...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： M.R. del Solar J.M.S. Perez J.A.G. Pulido M.A.V. Rodriguez Department de Informática Escuela Politécnica Caceres Spain

In this work we present a system for implementing the placement and routing stages in the FPGA cycle of design, into the physical design stage. We start with the ISCAS benchmarks, on EDIF format, of Boolean functions to be implemented. They are processed by a parser in order to obtain an internal representation which is able to be processed by a genetic algorithm (GA) tool. This tool develops the placement and routing tasks, considering possible restricted area into the FPGA. In order to help to the GA to make the routing stage we have added a local search procedure. That local search gets a path between two points without considering neither their placement nor the restricted areas among them. The GA is fully customizable, featuring the ability to work with one or several islands. The experiments have verified that using distributing execution improves the costs and speeds up the convergence towards better results in smaller slots of time

关键词： Routing Boolean functions Field programmable gate arrays Genetic algorithms Wire Circuits Biological cells Genetic programming Design automation Libraries

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A segment-based DSM supporting large shared object space 06

A segment-based DSM supporting large shared object space

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international symposium on parallel and Distributed Processing (IPDPS)

作者： B.W.-L. Cheung Cho-Li Wang Department of Computer Science University of Hong Kong Hong Kong China

ISBN: (纸本)9781424400546

This paper introduces a software DSM that can extend its shared object space exceeding 4GB in a 32-bit commodity cluster environment. This is achieved through the dynamic memory mapping mechanism, with local hard disks as backing store. We introduce the new concept of segments with intelligent splitting to reduce network traffic, false sharing as well as adapt better to the shared memory access patterns. A priority-based swapping algorithm is designed to reduce disk accesses for efficient dynamic memory mapping, and maximize the use of disk space as shared object space. A new queue-based scheme is also devised for efficient and simple management of memory blocks. The proposed solutions were implemented in LOTS V.2, and it can outperform its previous version when running small applications, while the maximum shared object space is increased to one-third of the total free disk space available among all the nodes

关键词： Application software programming profession Clustering algorithms Random access memory Computer science Hard disks Intelligent networks Telecommunication traffic Traffic control Algorithm design and analysis

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An evaluation of DELTA, a decoupled pre-fetching virtual shared memory system

An evaluation of DELTA, a decoupled pre-fetching virtual sha...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： I. Watson A. Rawsthorne M. Cumpstey F. Charpin Department Computer Science University of Manchester Institute of Science and Technology Manchester UK

Decoupled pre-fetching is a technique for reducing the page miss overheads in Distributed Shared Memory systems by separating out those instructions responsible for data fetching from the main instruction stream and running them on a separate CPU whose function is to predict store accesses ahead of time. This approach differs from other pre-fetching approaches in that the predictions of data usage are obtained dynamically from partial evaluation of the program and this promises to produce considerably better performance in circumstances where the access patterns are non-regular and cannot be extracted by static analysis of the program. This paper reviews the techniques of decoupled pre-fetching with particular emphasis on Cache only Memory architectures (COMA). It then presents a more thorough evaluation of the ideas than has previously been attempted using some of the SPLASH benchmarks. It is shown that the techniques perform well on some programs but that, as expected, the benefits of pre-fetching are negated when there is a high rate of data invalidation caused by global updating.

关键词： Memory architecture Yarn Switches Computer science Data mining Distributed decision making Delay programming profession Program processors Data structures

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Evaluation of Hybrid parallel Cell List algorithms For Monte Carlo Simulation

Evaluation of Hybrid Parallel Cell List Algorithms For Monte...

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IEEE international symposium on Cyberspace Safety and Security

作者： Kamel Rushaidat Loren Schwiebert Brock Jackman Jason Mick Jeffrey Potoff Department of Computer Science Wayne State University Department of Chemical Engineering and Materials Science Wayne State University

ISBN: (纸本)9781479989386

This paper describes efficient, scalable parallel implementations of the conventional cell list method and a modified cell list method to calculate the total system intermolecular Lennard-Jones force interactions in the Monte Carlo Gibbs ensemble. We targeted this part of the Gibbs ensemble for optimization because it is the most computationally demanding part of the force interactions in the simulation, as it involves all the molecules in the system. The modified cell list implementation reduces the number of particles that are outside the interaction range by making the cells smaller, thus reducing the number of unnecessary distance evaluations. Evaluation of the two cell list methods is done using a hybrid MPI+OpenMP approach and a hybrid MPI+CUDA approach. The cell list methods are evaluated on a small cluster of multicore CPUs, Intel Phi coprocessors, and GPUs. The performance results are evaluated using different combinations of MPI processes, threads, and problem sizes.

关键词： Cell List Monte Carlo Simulations Hybrid parallel architectures Gibbs Ensemble

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Implementation of an improved parallel code phase search algorithm for GPS signal acquisition on Zynq SoC

Implementation of an improved parallel code phase search alg...

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international symposium on Artificial Intelligence and Signal Processing (AISP)

作者： Amirreza Taghdiri Ali Moftakharzadeh Pouya Zahedi Hadi Safdarkhani dept. Electrical Engineering Yazd University Yazd Iran

In the field of Global Positioning System (GPS), signal acquisition stands as the initial and crucial step in the signal processing chain. Numerous algorithms have been proposed for acquisition, and this paper introduces enhancements to the parallel Code-phase Search (PCS) algorithm utilized for acquiring GPS satellite signals. Our approach involves the generation of carrier replica and PRN code, as well as the calculation of the FFT conjugate of the PRN code using MATLAB, with subsequent storage in an SD-Card. A key improvement lies in utilizing a single FFT IPCore for both FFT and IFFT computations, eliminating the need for two FFT IPCores and one IFFT IPCore as seen in the original PCS algorithm. This optimization results in reduced consumption of DSP blocks and memory resources. Furthermore, we compared different architectures, namely Radix-4, Radix-2, and Radix-2lite, in terms of clock cycles, resource utilization, and power consumption. The Radix-4 architecture was chosen due to its efficiency. This enhancement not only lowers power consumption by at least 8.8% but also increases the algorithm execution time while reducing overall costs.

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Experimental verification and benchmark of in-memory principal component analysis by crosspoint arrays of resistive switching memory

Experimental verification and benchmark of in-memory princip...

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IEEE international symposium on Circuits and Systems

作者： Piergiulio Mannocci Andrea Baroni Enrico Melacarne Cristian Zambelli Piero Olivo Eduardo Perez Christian Wenger Daniele Ielmini

ISBN: (数字)9781665484855

ISBN: (纸本)9781665484862

In-memory computing (IMC) is gaining momentum as the most promising candidate for the upcoming non-von-Neumann, machine learning-optimized computing paradigm. Its intrinsic parallelism is well-suited to accelerate matrix-vector multiplications (MVM), which prove challenging for traditional architectures and are a fundamental operation in principal component analysis (PCA), one of the most renowned algorithms for data classification. Here, we show an experimental demonstration of a novel, IMC-based PCA algorithm by in-memory power iteration and deflation executed in a 4-kbit array of resistive random-access memory (RRAM). Our algorithm achieves 95.25% classification accuracy on the Wisconsin Diagnostic Breast Cancer dataset, matching closely results of a floating-point machine while providing a 250 improvement in energy efficiency.

关键词： Semiconductor device modeling Machine learning algorithms Switches Computer architecture parallel processing In-memory computing Energy efficiency

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Fast multiplication of random dense matrices with sparse matrices

Fast multiplication of random dense matrices with sparse mat...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Tianyu Liang Riley Murray Aydın Buluç James Demmel Electrical Engineering and Computer Science Department UC Berkeley Computational Research Division Lawrence Berkeley National Lab International Computer Science Institute Sandia National Laboratories

ISBN: (数字)9798350387117

ISBN: (纸本)9798350387124

This work focuses on accelerating the multiplication of a dense random matrix with a (fixed) sparse matrix, which is frequently used in sketching algorithms. We develop a novel scheme that takes advantage of blocking and recomputation (on-the-fly random number generation) to accelerate this operation. The techniques we propose decrease memory movement, thereby increasing the algorithm’s parallel scalability in shared memory architectures. On the Intel Frontera architecture, our algorithm can achieve 2x speedups over libraries such as Eigen and Intel MKL on some examples. In addition, with 32 threads, we can obtain a parallel efficiency of up to 45%.We also present a theoretical analysis for the memory movement lower bound of our algorithm, showing that under mild assumptions, it’s possible to beat the data movement lower bound of general matrix-matrix multiply (GEMM) by a factor of M, where M is the cache size. Finally, we incorporate our sketching method into a randomized algorithm for overdetermined least squares with sparse data matrices. Our results are competitive with SuiteSparse for highly overdetermined problems; in some cases, we obtain a speedup of 10x over SuiteSparse.

关键词： Distributed processing Scalability Instruction sets Memory management Memory architecture Libraries Sparse matrices

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COMPOFF: A Compiler Cost model using Machine Learning to predict the Cost of OpenMP Offloading

COMPOFF: A Compiler Cost model using Machine Learning to pre...

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IEEE international symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Alok Mishra Smeet Chheda Carlos Soto Abid M. Malik Meifeng Lin Barbara Chapman Stony Brook University Stony Brook NY USA Brookhaven National Laboratory Upton NY USA

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

The HPC industry is inexorably moving towards an era of extremely heterogeneous architectures, with more devices configured on any given HPC platform and potentially more kinds of devices, some of them highly specialized. Writing a separate code suitable for each target system for a given HPC application is not practical. The better solution is to use directive-based parallel programming models such as OpenMP. OpenMP provides a number of options for offloading a piece of code to devices like GPUs. To select the best option from such options during compilation, most modern compilers use analytical models to estimate the cost of executing the original code and the different offloading code variants. Building such an analytical model for compilers is a difficult task that necessi-tates a lot of effort on the part of a compiler engineer. Recently, machine learning techniques have been successfully applied to build cost models for a variety of compiler optimization problems. In this paper, we present COMPOFF, a cost model that statically estimates the Cost of OpenMP OFFloading using a neural network model. We used six different transformations on a parallel code of Wilson Dslash Operator to support GPU offloading, and we predicted their cost of execution on different GPUs using COMPOFF during compile time. Our results show that this model can predict offloading costs with a root mean squared error in prediction of less than 0.5 seconds. Our preliminary findings indicate that this work will make it much easier and faster for scientists and compiler developers to port legacy HPC applications that use OpenMP to new heterogeneous computing environment.

关键词： Analytical models Costs Codes parallel programming Computational modeling Machine learning Predictive models

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A programming model for reconfigurable computing based in functional concurrency

A programming model for reconfigurable computing based in fu...

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international Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

作者： William L. Harrison Ian Graves Adam Procter Michela Becchi Gerard Allwein Department of Computer Science University of Missouri Department of Electrical & Computer Engineering University of Missouri US Naval Research Laboratory Washington DC

ISBN: (纸本)9781509025213

FPGA programmability remains a concern with respect to the broad adoption of the technology. One reason for this is simple: FPGA applications are frequently implementations of concurrent algorithms that could be most directly rendered in concurrent languages, but there is little or no first-class support for concurrent applications in conventional hardware description languages. It stands to reason that FPGA programmability would be enhanced in a hardware description language with first-class concurrency. The starting point for this paper is a functional hardware description language with built-in support for concurrency called ReWire. Because it is a concurrent functional language, ReWire supports the elegant expression of common concurrency paradigms; we illustrate this with several case studies.

关键词： Hardware Concurrent computing Clocks parallel processing programming Software engineering Computational modeling

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A new Co-evolutionary Algorithm Based on Constraint Decomposition

A new Co-evolutionary Algorithm Based on Constraint Decompos...

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IEEE international symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Emmanuel Kieffer Grégoire Danoy Pascal Bouvry Anass Nagih SnT Interdisciplinary Centre University of Luxembourg CSC Research Unit University of Luxembourg LCOMS Research Unit University of Lorraine France

Handling constraints is not a trivial task in evolutionary computing. Even if different techniques have been proposed in the literature, very few have considered co-evolution which tends to decompose problems into easier sub-problems. Existing co-evolutionary approaches have been mainly used to separate the decision vector. In this article we propose a different co-evolutionary approach, referred to as co-evolutionary constraint decomposition algorithm (CCDA), that relies on a decomposition of the constraints. Indeed, it is generally the conjunction of some specific constraints which hardens the problems. The proposed CCDA generates one sub-population for each constraint and optimizes its own local fitness. A sub-population will first try to satisfy its assigned constraint, then the remaining constraints from other sub-populations using a cooperative mechanism, and finally the original objective function. Thanks to this approach, sub-populations will have different behaviors and solutions will approach the feasible domain from different sides. An exchange of information is performed using crossover between individuals from different sub-populations while mutation is applied locally. Promising mutated features are then transmitted through mating. The proposed CCDA has been validated on 8 well-known benchmarks from the literature. Experimental results show the relevance of constraint decomposition in the context of co-evolution compared to state-of-the-art algorithms.

关键词： Sociology Statistics Optimization Genetic algorithms Decoding Predator prey systems Linear programming

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