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检索条件"任意字段=International Symposium on Parallel Architectures, Algorithms, and Programming"

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Offline Scheduling of Multi-threaded Request Streams on a Caching Server

Offline Scheduling of Multi-threaded Request Streams on a Ca...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Veronika Rehn-Sonigo Denis Trystram Frederic Wagner Haifeng Xu Guochuan Zhang Franche Comté University Besancon France Institut Universitaire de France Grenoble University France Grenoble University France University of Zhejiang Hangzhou China

In this work, we are interested in the problem of satisfying multiple concurrent requests submitted to a computing server. Informally, there are users each sending a sequence of requests to the server. The requests consist of tasks linked by precedence constraints. Tasks may occur several times in the same sequence as well as in a request sequence of another user. The computing server has to execute tasks with variable processing times. The server owns a cache of limited size where intermediate results of the processing may be stored. If an intermediate result for a task is stored into the cache, no processing cost has to be paid and the result can directly be fetched from the cache. The goal of this work is to determine a schedule of the tasks such that an optimization function is minimized (the only objective studied up to now is the make span). This problem is a variant of caching which considers only one sequence of requests. We then extend the study to the minimization of the mean completion time of the request sequences. Two models are considered. In the first model, caching is forced whereas in the second model caching is optional and one can choose whether an intermediate result is stored in the cache or not. All combinations turn out to be NP-hard for fixed cache sizes and we provide a formulation as dynamic program as well as bounds for in approximation. We propose polynomial time approximation algorithms for some variants and analyze their approximation ratios. Finally, we also devise some heuristics and present experimental results. Tasks may occur several times in the same sequence as well as in a request sequence of another user. The computing server has to execute tasks with variable processing times. The server owns a cache of limited size where intermediate results of the processing may be stored. If an intermediate result for a task is stored into the cache, no processing cost has to be paid and the result can directly be fetched from the cache. Th

关键词： Optimized production technology Servers Approximation algorithms Approximation methods Dynamic programming Schedules Heuristic algorithms

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Graphicionado: A high-performance and energy-efficient accelerator for graph analytics 49

Graphicionado: A high-performance and energy-efficient accel...

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IEEE/ACM international symposium on Microarchitecture (MICRO)

作者： Tae Jun Ham Lisa Wu Narayanan Sundaram Nadathur Satish Margaret Martonosi Princeton University University of California Berkeley Parallel Computing Lab Intel Corporation

ISBN: (纸本)9781509035090

Graphs are one of the key data structures for many real-world computing applications and the importance of graph analytics is ever-growing. While existing software graph processing frameworks improve programmability of graph analytics, underlying general purpose processors still limit the performance and energy efficiency of graph analytics. We architect a domain-specific accelerator, Graphicionado, for high-performance, energy-efficient processing of graph analytics workloads. For efficient graph analytics processing, Graphicionado exploits not only data structure-centric datapath specialization, but also memory subsystem specialization, all the while taking advantage of the parallelism inherent in this domain. Graphicionado augments the vertex programming paradigm, allowing different graph analytics applications to be mapped to the same accelerator framework, while maintaining flexibility through a small set of reconfigurable blocks. This paper describes Graphicionado pipeline design choices in detail and gives insights on how Graphicionado combats application execution inefficiencies on general-purpose CPUs. Our results show that Graphicionado achieves a 1.76-6.54x speedup while consuming 50-100x less energy compared to a state-of-the-art software graph analytics processing framework executing 32 threads on a 16-core Haswell Xeon processor.

关键词： Software programming Software algorithms Machine learning algorithms System-on-chip Pipelines Memory management

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Breadth-First Search on Heterogeneous Platforms: A Case of Study on Social Networks

Breadth-First Search on Heterogeneous Platforms: A Case of S...

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international symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

作者： Luis Remis Maria Jesus Garzaran Rafael Asenjo Angeles Navarro Universidad de Málaga Spain Department of Computer Science University of Illinois at Urbana Champaign Intel Corp.

ISBN: (纸本)9781509061099

Breadth-First Search (BFS) is the core of many graph analysis algorithms and it is used in many problems, such as social network, computer network analysis, and data organization. BFS is an iterative algorithm that due to its irregular behavior is quite challenging to parallelize. Several approaches implement efficient algorithms for BFS for multicore architectures and for Graphics Processors, but it is still an open problem how to distribute the work among the main cores and the accelerators. In this paper, we assess several approaches to perform BFS on different heterogenous architectures (highend and embedded mobile processors composed of a multi-core CPU and an integrated GPU) with a focus on social network graphs. In particular, we propose two heterogenous approaches to exploit both devices. The first one, called Selective, selects on which device to execute each iteration. It is based on a previous approach, but we have adapted it to take advantage of the features of social network graphs (fewer iterations but more unbalanced). The second approach, referred as Concurrent, allows the execution of specific iterations concurrently in both devices. Our heterogenous implementations can be up to 1.56x faster and 1.32x more energy efficient with respect to the best of only-CPU or only-GPU baselines. We have also found that for a highly memory bound problem like BFS, the CPU-GPU collaborative execution is limited by the shared-memory bus bandwidth.

关键词： Graphics processing units Social network services Algorithm design and analysis Multicore processing Roads parallel processing

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A simple library and basic code for LUC Cryptosystem computation

A simple library and basic code for LUC Cryptosystem computa...

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international symposium on Information Technology, ITSim

作者： Zulkarnain Md Ali Mohamed Othman Mohd Rushdan Mohd Said Mohammad Nasir Sulaiman Department of Computer Science UKM Bangi Selangor Darul Ehsan Malaysia Department of Communication and Network Technology UPM Serdang Selangor Darul Ehsan Malaysia Department of Mathematics UPM Serdang Selangor Darul Ehsan Malaysia Department of Computer Science UPM Serdang Selangor Darul Ehsan Malaysia

The LUC Cryptosystem is one of public key cryptosystem. Both encryption and decryption process will use Lucas Function as its computation technique. At the moment, we are already developed a fast computation techniques for LUC Cryptosystem. The comparisons of the techniques are done by an analysis on its computation technique and computation time. In this paper, we are concentrating on using C language as our main programming language when we design proposed algorithms. To support the suitable C codes for that algorithm, we will design our own C library. Therefore, we will show a simple C library and its suitable codes that could represent the algorithm. We will also show the effectiveness of this library and its limitation that can be improved later.

关键词： Cryptography Libraries Algorithm design and analysis Public key cryptography Equations parallel algorithms Binary sequences

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Towards performance portability of AI graphs using SYCL

Towards performance portability of AI graphs using SYCL

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Performance, Portability and Productivity in HPC (P3HPC)

作者： Kumudha Narasimhan Ouadie El Farouki Mehdi Goli Muhammad Tanvir Svetlozar Georgiev Isaac Ault Codeplay Software Ltd. Edinburgh UK

ISBN: (纸本)9781665460224

The wide adoption of Deep Neural Networks (DNN) has served as an incentive to design and manufacture powerful and specialized hardware technologies, targeting systems from Edge devices to Cloud and *** the proposed ONNX as a de facto for DNN model description, provides portability across various AI frameworks, supporting DNN models on various hardware architectures remains *** provides a C++-based portable parallel programming model to target various devices. Thus, enabling SYCL backend for an AI framework can lead to a hardware-agnostic model for heterogeneous *** paper proposes a SYCL backend for ONNXRuntime as a possible solution towards the performance portability of deep learning algorithms. The proposed backend uses existing state-of-the-art SYCL-DNN and SYCL-BLAS libraries to invoke tuned SYCL kernels for DNN operations. Our performance evaluation shows that the proposed approach can achieve comparable performance with respect to the state-of-the-art optimized vendor-specific libraries.

关键词： Performance evaluation Deep learning Productivity Runtime parallel programming Neural networks Libraries

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Boosting Memory Performance of Many-Core FPGA Device through Dynamic Precedence Graph

Boosting Memory Performance of Many-Core FPGA Device through...

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Annual IEEE symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Yu Bai Abigail Fuentes Michael Riera Mohammed Alawad Mingjie Lin Department of Electrical Engineering and Computer Science University of Central Florida Orlando FL USA

Emerging FPGA device, integrated with abundant RAM blocks and high-performance processor cores, offers an unprecedented opportunity to effectively implement single-chip distributed logic-memory (DLM) architectures [1]. Being “memory-centric”, the DLM architecture can significantly improve the overall performance and energy efficiency of many memory-intensive embedded applications, especially those that exhibit irregular array data access patterns at algorithmic level. However, implementing DLM architecture poses unique challenges to an FPGA designer in terms of 1) organizing and partitioning diverse on-chip memory resources, and 2) orchestrating effective data transmission between on-chip and off-chip memory. In this paper, we offer our solutions to both of these challenges. Specifically, 1) we propose a stochastic memory partitioning scheme based on the well-known simulated annealing algorithm. It obtains memory partitioning solutions that promote parallelized memory accesses by exploring large solution space; 2) we augment the proposed DLM architecture with a reconfigure hardware graph that can dynamically compute precedence relationship between memory partitions, thus effectively exploiting algorithmic level memory parallelism on a per-application basis. We evaluate the effectiveness of our approach (A3) against two other DLM architecture synthesizing methods: an algorithmic-centric reconfigurable computing architectures with a single monolithic memory (A1) and the heterogeneous distributed architectures synthesized according to [1] (A2). To make our comparison fair, in all three architectures, the data path remains the same while local memory architecture differs. For each of ten benchmark applications from SPEC2006 and MiBench [2], we break down the performance benefit of using A3 into two parts: the portion due to stochastic local memory partitioning and the portion due to the dynamic graph-based memory arbitration. All experiments have been conducted with a V

关键词： Random access memory Field programmable gate arrays Computer architecture Heuristic algorithms Hardware Partitioning algorithms parallel processing

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State-of-the-art of the wafer scale ELSA project

State-of-the-art of the wafer scale ELSA project

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IEEE international symposium on Defect and Fault Tolerance in VLSI Systems

作者： A. Boubekeur J.-I. Patry G. Saucier J. Trilhe I.N.P.G/CSI Grenoble France SGS-Thomson Microelectronics Grenoble France

ELSA project concerns massively parallel architectures on silicon dedicated especially to low-level image processing. Real-time low-level image processing demands a huge amount of computing power. Fortunately, the algorithms encountered in this field are naturally regular which suggests a regular architecture to solve them. One of the most efficient scheme is array processors. This array processor has been implemented on a whole wafer instead of implementing it in VLSI chips each containing a few processing elements. Potential advantages of wafer scale integration over conventional VLSI systems include lower power, higher speed and small volume. However, WSI suffers from low yield. Redundancy and reconfiguration techniques are used to enhance the overall yield. Both of these have been implemented in ELSA. Three software packages have been developed to completely (re)configure the wafer and build a working target array.< >

关键词： Switches Computer architecture Image processing Very large scale integration Software packages parallel architectures Silicon Wafer scale integration Rails Joining processes

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Two-dimensional recursive digital filtering: pipelining, one- and two-dimensional block processing

Two-dimensional recursive digital filtering: pipelining, one...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： K.K. Parhi D.G. Messerschmitt Department of Electrical Engineering and Computer Science University of California Berkeley CA USA

Unlike one-dimensional recursive systems, two-dimensional recursive digital filter algorithms possess a large amount of inherent concurrency which can be exploited for pipelining and/or parallelism. The locus of these concurrent computations is referred to as the concurrent computation region. The authors describe the use of this concurrency to derive pipelined and one-dimensional block architecture for implementation of two-dimensional recursive digital filters by appropriate interleaving (or indexing) of the input samples, without requiring any algorithm transformation and without any hardware overhead. They also derive a two-dimensional incremental block filter using look-ahead computation and incremental computation techniques. Pipelined two-dimensional block structures and the index mapping functions for various architectures are presented. Finally, it is shown that for an N-dimensional recursive filter, the concurrent computation region corresponds to an (N-1)-dimensional hyperplane.< >

关键词： Digital filters Filtering Pipeline processing Concurrent computing Interleaved codes Indexing Sampling methods Delay parallel processing Computer architecture

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Optimizing Memory Access in TCF Processors with Compute-Update Operations

Optimizing Memory Access in TCF Processors with Compute-Upda...

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IEEE international symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Martti Forsell Jussi Roivainen Jesper Larsson Träff VTT Faculty of Informatics Vienna University of Technology

ISBN: (数字)9781728174457

ISBN: (纸本)9781728174570

The thick control flow (TCF) model is a data parallel abstraction of the thread model. It merges homogeneous threads (called fibers) flowing through the same control path to entities (called TCFs) with a single control flow and multiple data flows. Fibers of a TCF are executed synchronously with respect to each other and the number of them can be altered dynamically at runtime. Multiple TCFs can be executed in parallel to support control parallelism. In our previous work, we have outlined a special architecture, TPA (Thick control flow Processor Architecture), for executing TCF programs efficiently and shown that designing algorithms with the TCF model often leads to increased performance and simplified programs due to higher abstraction, eliminated loops and redundant program ***-update memory operations, such as multioperations and atomic instructions, are known to speed up parallel algorithms performing reductions and synchronizations. In this paper, we propose special compute-update memory operations for TCF processors to optimize iterative exclusive inter-fiber memory access patterns. Acceleration is achieved, e.g., in matrix addition and log-prefix style patterns in which multiple target locations can interchange data without reloads between the instructions that slows down execution. Our solution is based on modified active memory units and special memory operations that can send their reply value to another fiber than that initiating the access. We implement these operations in our TPA processor with a minimal HW cost and show that the expected speedups are achieved. programming examples are given.

关键词： Instruction sets Optical fiber networks parallel processing Memory management Computational modeling

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Network on Chip and parallel Computing in Embedded Systems

Network on Chip and Parallel Computing in Embedded Systems

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IEEE international symposium on Embedded Multicore Socs (MCSoC)

作者： Dihia Belkacemi Youcef Bouchebaba Mehammed Daoui Mustapha Lalam Laboratoire de Recherche en Informatique Université de Tizi-Ouzou Algeria ONERA-Toulouse France

ISBN: (纸本)9781509035328

In order to cope with the increasing application requirements, heterogeneous MPSoC are considered as the major solution of future embedded systems thanks to their advantages in performance and low power dissipation. However traditional communication infrastructure such as a bus or a point to point are not scalable and become communication bottleneck for large systems. Network on chip (NoC) architectures have been proposed to handle this communication problem. One of the most critical problem in NoC based heterogeneous MPSoC is how to map an application on this platform. Due to the large solution search space, design of tools that can automate this step is of major importance. In this paper, we present a new tool for mapping applications on NoC based heterogeneous MPSoC. A set of multi-objective optimization algorithms are used to explore the mapping space and to find a set of Pareto optimal solutions.

关键词： Program processors Cost function Energy consumption Memory management Encoding

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