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Annual IEEE symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Glenn G. Ko Yuji Chai Rob A. Rutenbar David Brooks Gu-Yeon Wei Harvard University Cambridge USA University of Illinois at Urbana-Champaign Urbana USA University of Pittsburgh Pittsburgh USA

Many consider one of the key components to the success of deep learning as its compatibility with existing accelerators, mainly GPU. While GPUs are great at handling linear algebra kernels commonly found in deep learning, they are not the optimal architecture for handling unsupervised learning methods such as Bayesian models and inference. As a step towards, achieving better understanding of architectures for probabilistic models, Gibbs sampling, one of the most commonly used algorithms for Bayesian inference, is studied with a focus on parallelism that converges to the target distribution and parameterized components. We propose FlexGibbs, a reconfigurable parallel Gibbs sampling inference accelerator for structured graphs. We designed an architecture optimal for solving Markov Random Field tasks using an array of parallel Gibbs samplers, enabled by chromatic scheduling. We show that for sound source separation application, FlexGibbs configured on the FPGA fabric of Xilinx Zync CPU-FPGA SoC achieved Gibbs sampling inference speedup of 1048x and 99.85% reduction in energy over running it on ARM Cortex-A53.

关键词： Bayes methods Markov processes Source separation Hardware Acceleration Deep learning

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A graph-theoretic sufficient condition for FPGA/FPIC switch-module routability

A graph-theoretic sufficient condition for FPGA/FPIC switch-...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Yao-Wen Chang D.F. Wong C.K. Wong Department of Computer and Information Science National Chiao Tung University Hsinchu Taiwan Department of Computer Sciences University of Texas Austin Austin TX USA Department of Computer Science Chinese University of Hong Kong Hong Kong China

Switch modules are the most important component of the routing resources in FPGAs/FPICs. We consider in this paper an FPGA/FPIC switch-module analyse's problem: The inputs consist of a switch-module description and the number of nets required to be routed through the switch module; the question is to determine if there exists a feasible routing for the routing requirements on the switch module. This problem is applicable to the routability evaluation of FPGA/FPIC switch modules, the switch-module design for FPGAs/FPICs, and FPGA/FPIC routing. We present a graph-theoretic sufficient condition for the analyse's problem. The implications of the condition are: (1) there exist several classes of efficient approximation algorithms for the analysis problem; (2) there exist several classes of switch-module architectures on which the analysis problem can be solved efficiently.

关键词： Sufficient conditions Field programmable gate arrays Switches Routing Logic circuits Logic programming Integrated circuit interconnections Algorithm design and analysis Logic arrays Pins

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Global events and global breakpoints in distributed systems

Global events and global breakpoints in distributed systems

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Annual Hawaii international Conference on System Sciences (HICSS)

作者： D. Haban W. Weigel Department of Computer Science INCAS-Project SFB 124 University of Kaiserslautem Kaiserslautern Germany

A solution to the problem of setting breakpoints in distributed systems is described. It is shown what kind of breakpoints are possible, how to detect those breakpoints, and how to halt the system in a consistent state. The communication among the processes may be asynchronous with an arbitrary ordering of messages. The algorithms select between simultaneous events and those ordered according to L. Lamport's happened-before relation (1978). The mechanisms for definition and detection of global breakpoints are implemented in the distributed debugging system DTM (distributed test methodology).< >

关键词： Debugging Computer science programming profession Message passing Topology Delay effects Centralized control Communication system control Very large scale integration parallel architectures

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Multi-science applications with single codebase — GAMER — For massively parallel architectures

Multi-science applications with single codebase — GAMER — ...

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Supercomputing Conference

作者： Hemant Shukla Tak-Pong Woo Hsi-Yu Schive Tzihong Chiueh Lawrence Berkeley National laboratory Berkeley USA Department of Physics National Taiwan University Taipei Taiwan Department of Physics Soochow University Taipei Taiwan

The growing need for power efficient extreme-scale high-performance computing (HPC) coupled with plateauing clock-speeds is driving the emergence of massively parallel compute architectures. Tens to many hundreds of cores are increasingly made available as compute units, either as the integral part of the main processor or as coprocessors designed for handling massively parallel workloads. In the case of many-core graphics processing units (GPUs) hundreds of SIMD cores primarily designed for image and video rendering are used for high-performance scientific computations. The new architectures typically offer ANSI standard programming models such as CUDA (NVIDIA) and OpenCL. However, the wide-ranging adoption of these parallel architectures is steeped in difficult learning curve and requires reengineering of existing applications that mostly leads to expensive and error prone code rewrites without prior guarantee and knowledge of any speedups. Broad range of complex scientific applications across many domains use common algorithms and techniques, such as adaptive mesh refinements (AMR), advanced hydrodynamics partial differential equation (PDE) solvers, Poisson-Gravity solvers etc, that have demonstrably performed highly efficiently on GPU based systems. Taking advantage of the commonalities, we use GPU-aware AMR code, GAMER [1], to examine the unique approach of solving multi-science problems in astrophysics, hydrodynamics and particle physics with single codebase. We demonstrate significant speedups in disparate class of scientific applications on 3 separate clusters, viz., Dirac, Laohu and Mole 8.5. By extensively reusing the extendable single codebase we mitigate the impediments of significant code rewrites. We also collect performance and energy consumption benchmark metrics on 50-nodes NVIDIA C2050 GPU and Intel 8-core Nehalem CPU on Dirac cluster at the National Energy Research Supercomputing Center (NERSC). In addition, we propose a strategy and framework for

关键词： Graphics processing unit Kernel Computational modeling Instruction sets Mathematical model Memory management

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Automatic generation of passive equivalent circuits for broadband microstrip antennas

Automatic generation of passive equivalent circuits for broa...

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Antennas and Propagation Society international symposium

作者： Yi-Ting Kuo Hsueh-Yung Chao Yiming Li High-Frequency EDA Laboratory Department of Communication Engineering National Chiao Tung University Hsinchu Taiwan Parallel and Scientific Computing Laboratory Department of Communication Engineering National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)9781424408771;1424408776

In this paper, we propose an efficient method for extracting passive equivalent circuits of broadband antennas. To fully automate the extraction, the vector fitting in B. Gustaven and A. Semlyen (1999) is modified such that the order of the rational approximation can be determined automatically for a given error bound. Then, the approximation is corrected by quadratic programming for enforcing passivity. The passive model is further synthesized by RLC components using algorithms in G. Antonini (2003). As a result, simulated or measured frequency responses of a broadband antenna can be fit with minimum fitting error over a wide range of frequencies.

关键词： Microstrip antennas Broadband antennas Equivalent circuits Dipole antennas Frequency Microstrip components Laboratories Radiofrequency integrated circuits Circuit simulation Antenna accessories

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Workshop 13: PDSEC parallel and Distributed Scientific and Engineering Computing

Workshop 13: PDSEC Parallel and Distributed Scientific and E...

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IEEE international symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Raphaël Couturier Peter Strazdins Eric Aubanel Sabine Roller Laurence T. Yang Thomas Rauber Gudula Runger University of Franche-Comté France The Australian National University Australia University of New Brunswick Canada University of Siegen Germany St. Francis Xavier University Canada University of Bayreuth Germany Chemnitz University of Technology Germany

ISBN: (数字)9781728174457

ISBN: (纸本)9781728174570

Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. The technological trends in HPC system evolution indicates an increasing burden placed on application developers due to the management of the unprecedented complexity levels of hardware and its associated performance characteristics. Many existing scientific applications codes are unlikely to perform well on future systems without major modifications or even complete rewrites. In the future, it will be necessary to utilize, in concert, many characteristics such as multiple levels of parallelism, many lightweight cores, complex memory hierarchies, novel I/O technology, power capping, system-wide temporal/spatial performance heterogeneity and reliability concerns. The parallel and distributed computing (PDC) community has developed new programming models, algorithms, libraries and tools to meet these challenges in order to accommodate productive code development and effective system use. However, the scientific application community still needs to identify the benefit through practical evaluations. Thus, the focus of this workshop is on methodologies and experiences used in scientific and engineering applications and algorithms to achieve sustainable code development for better productivity, application performance and reliability.

关键词： Handheld computers Reliability Distributed processing Market research

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AFFORDe: Automatic Allocation and Floorplanning for SPMD Architecture

AFFORDe: Automatic Allocation and Floorplanning for SPMD Arc...

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IEEE international symposium on Embedded Multicore Socs (MCSoC)

作者： Wissem Chouchene Rabie Ben Atitallah Jean-Luc Dekeyser CRISTAL University of Lillel Lille France LAMIH University of Valenciennes Valenciennes France

ISBN: (纸本)9781509035328

Nowadays, Field Programmable Gate Arrays (FPGAs) platforms offer a high density to allow designing Multi Processor-based System on Chip. SPMD (Single Program Multiple Data) is a massively parallel execution model based on the assembly of a given number of homogeneous Processing Elements (PEs). This model is often relaying on Master/Slaves architecture composed by a Master PE that manages the parallel execution of a set of identical slave PEs. Furthermore, Dynamic Partial Reconfiguration (DPR) feature allows such computing system to be reconfigured on the fly for a given application requirement. Given the growing number of PEs in Master/Slaves architecture, it is difficult to estimate the time of specification and design during the phase of allocation and floorplanning of Partial Reconfigurable Regions (PRRs) because it is still performed manually. In this work, we present AFFORDe, a tool enable to automate the Xilinx DPR flow for SPMD architecture that allows parsing the resource requirements of the static and the dynamically reconfigurable parts to perform an automatic floorplanning. The floorplanning is based on a Heuristic Algorithm for Automatic Floorplanning in SPMD architectures (HAAFSA). This tool is used to generate a configuration file that allows floorplanning of reconfigurable regions in an automatic way of a given Master/Slaves configuration. Experimental results show the effectiveness of our tool to increase the design productivity for dynamically reconfigurable SPMD-based architecture.

关键词： Field programmable gate arrays Computer architecture Heuristic algorithms Algorithm design and analysis Automation parallel processing Optimization

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Time-constrained code compaction for DSPs

Time-constrained code compaction for DSPs

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international symposium on System Synthesis

作者： R. Leupers P. Marwedel Department of Computer Science XII University of Dortmund Dortmund Germany

DSP algorithms are, in most cases, subject to hard real-time constraints. In the case of programmable DSPs, meeting those constraints must be ensured by appropriate code generation techniques. For processors offering instruction-level parallelism, the task of code generation includes code compaction. The exact timing behavior of a DSP program is only known after compaction. Therefore, real-time constraints should be taken into account during the compaction phase. While most known DSP code generators rely on rigid heuristics for that phase, this paper proposes a novel approach to local code compaction based on an integer programming model, which obeys exact timing constraints. Due to a general problem formulation, the model also obeys encoding restrictions and possible side-effects.

关键词： Compaction Digital signal processing Timing Time factors Constraint optimization Instruction sets Registers Hardware Computer science parallel processing

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Asynchronous parallel Evolutionary algorithms for Optimizations

Asynchronous Parallel Evolutionary Algorithms for Optimizati...

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2001 international symposium on Distributed Computing and Applications to Business, Engineering and Science

作者： Hugo de Garis Starlab Brain Builder Group

Recently we proposed a Robust Evolutionary Algorithm for solving nonlinear programming(NLP) problems[4].It is an extension of Guo's algorithm[1],which possesses enhanced capabilities for solving NLP *** capabilities include:a) advancing the variable subspace,b) adding a search process over subspaces and normalized constraints,c) using an adaptive penalty function,and d) adding the ability to deal with integer NLP problems.0-1 NLP problems,and mixed-integer NLP problems which have equality *** this paper an asynchronous parallel evolutionary algorithm with scalable granularities for MIMD machines is designed by parallelizing the Robust Evolutionary Algorithm.A challenge NLP problem is chosen as the test *** experiments show that the new algorithm is very efficient and effective.

关键词： parallel algorithm Evolutionary Computation function optimization

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Exploring one-sided communication and synchronization on a non-cache-coherent many-core architecture

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2017年第15期29卷

作者： Christgau, Steffen Schnor, Bettina Univ Potsdam Inst Comp Sci August Bebel Str 89 D-14482 Potsdam Germany

The ongoing many-core design aims at core counts where cache coherence becomes a serious challenge. Therefore, this paper discusses how one-sided communication and the required process synchronization can be realized on a non-cache-coherent many-core CPU. The Intel Single-chip Cloud Computer serves as an exemplary hardware architecture. The presented approach is based on software-managed cache coherence for MPI one-sided communication. The prototype implementation delivers a PUT performance of up to 5 times faster than the default message-based approach and reveals a reduction of the communication costs for the NAS parallel Benchmarks 3-D fast Fourier Transform by a factor of 5. Further, the paper derives conclusions for future non-cache-coherent architectures.

关键词： MPI one-sided communication programming models and systems for many-cores synchronization software-managed cache coherence

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