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检索条件"任意字段=International Symposium on Parallel Architectures, Algorithms, and Programming"

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An Aggregated Ant Colony Optimization approach for pricing options

An Aggregated Ant Colony Optimization approach for pricing o...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Yeshwanth Udayshankar Sameer Kumar Girish K. Jha Ruppa K. Thulasiram Parimala Thulasiraman Department of Computer Science University of Manitoba Winnipeg MAN Canada

Estimating the current cost of an option by predicting the underlying asset prices is the most common methodology for pricing options. Pricing options has been a challenging problem for a long time due to unpredictability in market which gives rise to unpredictability in the option prices. Also the time when the options have to be exercised has to be determined to maximize the profits. This paper proposes an algorithm for predicting the time and price when the option can be exercised to gain expected profits. The proposed method is based on Nature inspired algorithm i.e. Ant Colony Optimization (ACO) which is used extensively in combinatorial optimization problems and dynamic applications such as mobile ad-hoc networks where the objective is to find the shortest path. In option pricing, the primary objective is to find the best node in terms of price and time that would bring expected profit to the investor. Ants traverse the solution space (asset price movements) in the market to identify a profitable node. We have designed and implemented an Aggregated ACO algorithm to price options which is distributed and robust. The initial results are encouraging and we are continuing this work further.

关键词： Ant colony optimization Pricing Genetic programming Finance Neural networks Portfolios Contracts Computational intelligence Genetic algorithms Computer science

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Continuous compilation: a new approach to aggressive and adaptive code transformation

Continuous compilation: a new approach to aggressive and ada...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： B. Childers J.W. Davidson M.L. Soffa Department of Computer Science University of Pittsburgh Pittsburgh PA USA Department of Computer Science University of Virginia Charlottesville VA USA

Over the past several decades, the compiler research community has developed a number of sophisticated and powerful algorithms for a variety of code improvements. While there are still promising directions for particular optimizations, research on new or improved optimizations is reaching the point of diminishing returns and new approaches are needed to achieve significant performance improvements beyond traditional optimizations. In this paper, we describe a new strategy based on a continuous compilation system that constantly improves application code by applying aggressive and adaptive code optimizations at all times, from static optimization to online dynamic optimization. In this paper, we describe our general approach and process for continuous compilation of application code. We also present initial results from our research with continuous compilation. These initial results include a new prediction framework that can estimate the benefit of applying code transformations without actually doing the transformation. We also describe results that demonstrate the benefit of adaptively changing application code for embedded systems to make trade-offs between code size, performance, and power consumption.

关键词： Adaptive coding Phase estimation Power system planning Computer science Runtime Dynamic programming Lifting equipment Distributed processing Embedded system Cost function

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Optimizations and Analysis of BSP Graph Processing Models on Public Clouds

Optimizations and Analysis of BSP Graph Processing Models on...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Mark Redekopp Yogesh Simmhan Viktor K. Prasanna University of Southern California Los Angeles CA USA

ISBN: (纸本)9781467360661

Large-scale graph analytics is a central tool in many fields, and exemplifies the size and complexity of Big Data applications. Recent distributed graph processing frameworks utilize the venerable Bulk Synchronous parallel (BSP) model and promise scalability for large graph analytics. This has been made popular by Google's Pregel, which provides an architecture design for BSP graph processing. Public clouds offer democratized access to medium-sized compute infrastructure with the promise of rapid provisioning with no capital investment. Evaluating BSP graph frameworks on cloud platforms with their unique constraints is less explored. Here, we present optimizations and analyses for computationally complex graph analysis algorithms such as betweenness-centrality and all-pairs shortest paths on a native BSP framework we have developed for the Microsoft Azure Cloud, modeled on the Pregel graph processing model. We propose novel heuristics for scheduling graph vertex processing in swaths to maximize resource utilization on cloud VMs that lead to a 3.5x performance improvement. We explore the effects of graph partitioning in the context of BSP, and show that even a well partitioned graph may not lead to performance improvements due to BSP's barrier synchronization. We end with a discussion on leveraging cloud elasticity for dynamically scaling the number of BSP workers to achieve a better performance than a static deployment, and at a significantly lower cost.

关键词： Cloud computing Algorithm design and analysis Scalability programming Computational modeling Optimization Synchronization

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Graphite: A distributed parallel simulator for multicores

Graphite: A distributed parallel simulator for multicores

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IEEE symposium on High-Performance Computer Architecture

作者： Jason E. Miller Harshad Kasture George Kurian Charles Gruenwald Nathan Beckmann Christopher Celio Jonathan Eastep Anant Agarwal Massachusetts Institute of Technology Cambridge MA USA

This paper introduces the Graphite open-source distributed parallel multicore simulator infrastructure. Graphite is designed from the ground up for exploration of future multi-core processors containing dozens, hundreds, or even thousands of cores. It provides high performance for fast design space exploration and software development. Several techniques are used to achieve this including: direct execution, seamless multicore and multi-machine distribution, and lax synchronization. Graphite is capable of accelerating simulations by distributing them across multiple commodity Linux machines. When using multiple machines, it provides the illusion of a single process with a single, shared address space, allowing it to run off-the-shelf pthread applications with no source code modification. Our results demonstrate that Graphite can simulate target architectures containing over 1000 cores on ten 8-core servers. Performance scales well as more machines are added with near linear speedup in many cases. Simulation slowdown is as low as 41× versus native execution.

关键词： Multicore processing Computational modeling Computer architecture programming Open source software Application software Hardware Acceleration Linux Performance evaluation

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Phloem: Automatic Acceleration of Irregular Applications with Fine-Grain Pipeline parallelism

Phloem: Automatic Acceleration of Irregular Applications wit...

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IEEE symposium on High-Performance Computer Architecture

作者： Quan M. Nguyen Daniel Sanchez MIT CSAIL

Irregular applications are increasingly common in diverse domains, like graph analytics and sparse linear algebra. Accelerating these applications is challenging because of their unpredictable data reuse and control flow. Recent work has proposed hardware support for fine-grain pipeline parallelism, hiding long latencies by decoupling irregular applications into pipeline stages. However, this prior work requires programmers to manually decouple applications. This tedious and error-prone process limits the usefulness of such architectural *** address this problem with Phloem, a compiler that automatically discovers and exploits pipeline parallelism in irregular applications. Prior compilers for pipeline parallelism target regular applications, which contain simple pipeline stages with known latencies and fixed buffering needs. Designing Phloem to target irregular applications, where these properties do not hold, requires treating their unique challenges as first-class considerations throughout its design. Phloem breaks down this complex transformation into a series of simple passes that together encode the insights that have been previously applied by hand, producing code that targets architectures with support for queue-based *** evaluate Phloem by generating efficient pipelines on a variety of irregular applications. Phloem’s contributions improve performance by 1.7× on average, approaching (and sometimes exceeding) the performance of manually optimized pipeline-parallel code. These results show that, for the first time, automatic parallelization for irregular applications is not only feasible, but also profitable.

关键词： Codes Pipelines Computer architecture Transforms Linear algebra parallel processing programming

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Comparison of three different architectures for MOS-compatible quadratic synapses

Comparison of three different architectures for MOS-compatib...

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international symposium on Speech, Image Processing and Neural Networks

作者： S.M. Fakhraie K.C. Smith J.M. Xu Department of Electrical and Computer Engineering University of Toronto Toronto ONT Canada Department of Electrical and Electronics Engineering Hong Kong University of Science and Technology Hong Kong China

Inspired by the harmony between the basic functional elements of biological neural networks and their natural operating media, we have been seeking for ways to implement artificial neural networks (ANNs) using the intrinsic functionality of the most commonly available devices in an electronics technology, in contrast to the method of hardware-compilation of software-simulation modules. In the case of MOS technology, we employ a quadratic functional equation similar to that found in standard MOS transistors to implement synapses in ANNs. A structure has been proposed in to implement a MOS device with externally-controllable threshold voltage to be employed as a synapse. In the present work, we develop and compare practical architectures within which these synapses can be utilized optimally. A simulator and proper training algorithms have been developed to simulate different hardware-based architectures.< >

关键词： Equations Computer architecture MOSFETs Threshold voltage Artificial neural networks MOS devices parallel processing Hardware Voltage control CMOS technology

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Application-Oriented On-Board Software Management System for Micro-Nano Satellite

Application-Oriented On-Board Software Management System for...

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IEEE international symposium on Geoscience and Remote Sensing (IGARSS)

作者： Yuan Yao Lantian Chang Xiaojie Yu Haopeng Zhang DFH Satellite Co. Ltd. Beijing China School of Astronautics Beihang University Beijing China Tianmushan Laboratory Hangzhou China

ISBN: (数字)9798350360325

ISBN: (纸本)9798350360332

The traditional on-board software architecture lacks adaptability and scalability, with a high degree of customization, significant software-hardware coupling, and slow technological evolution. To enhance utilization efficiency and intelligent application capabilities of satellite, this paper proposes an application-oriented on-board software management system for micro-nano satellite. By analyzing the research status and technical characteristics of traditional software architectures, an open software management system based on Linux is implemented, including key components and functions. In line with the system’s operational mode, we propose a method for on-board software dynamic refactoring. Furthermore, we validate the effectiveness of the software management system by a remote sensing image processing algorithm, which has a wide application prospect.

关键词： Satellites Software architecture Scalability Linux Software algorithms Computer architecture parallel processing

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A Configuration Control Mechanism Based on Concurrency Level for a Reconfigurable Consistency Algorithm

A Configuration Control Mechanism Based on Concurrency Level...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Christiane V. Pousa Luis F. W. Goes Carlos A. P. S. Martins Computational and Digital Systems Group Pontifical Catholic University of Minas Gerais Belo Horizonte Brazil Computational and Digital Systems Group Pontifical Catholic University of Minas Gerais Belo Brazil

A Reconfigurable Consistency Algorithm (RCA) is an algorithm that guarantees the consistency in Distributed Shared Memory (DSM) Systems. In a RCA, there is a Configuration Control Layer (CCL) that is responsible for selecting the most suitable RCA configuration (behavior) for a specific workload and DSM system. In previous works, we defined an upper bound performance for RCA based on an ideal CCL, which knows apriori the best configuration for each situation. This ideal CCL is based on a set of workloads characteristics that, in most situations, are difficult to extract from the applications (percentage of shared write and read operations and sharing patterns). In this paper we propose, develop and present a heuristical configuration control mechanism for the CCL implementation. This mechanism is based on an easily obtained applications parameter, the concurrency level. Our results show that this configuration control mechanism improves the RCA performance in 15%, on average, compared to other traditional consistency algorithms. Furthermore, the CCL with this mechanism is independent from the workload and DSM system specific characteristics, like sharing patterns and percentage of writes and reads.

关键词： Concurrent computing Control systems Distributed computing Digital systems Algorithm design and analysis Upper bound Contracts parallel programming Operating systems Performance analysis

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parallel processing and simulation: a panel discussion 82

Parallel processing and simulation: a panel discussion

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Proceedings of the 14th conference on Winter Simulation - Volume 2

作者： James G. Smith John C. Comfort J. Misra Ann Hayes George Fishman Office of Naval Research Arlington Virginia Florida International University Miami Florida University of Texas Austin Texas Los Alamos National Laboratory Los Alamos New Mexico University of North Carolina Chapel Hill North Carolina

Approaching rapidly on the horizon is a change to parallel architecture in digital computers that has the potential for multiplying the speed of execution achieved in serial architectures. The departure from serial operations provides rather obvious improvements in execution times for operations that are repetitive and that can be performed independently of each other. Such operations arise frequently in signal processing programs and in mathematical programming algorithms. Of interest to this conference is the impact of the new architectures on the practice of simulation - particularly simulations of large physical systems. A large number of questions can be raised (but few answered) on the impact of the new machines on simulation model designs, languages, data base manipulation, and other questions on the general utility of such machines for simulation problem solving. Moreover, it is likely that the new machines will influence the design of simulation experiments, random number generation, strategies for statistical iterations, sensitivity analyses, and variance reduction methods. Because of the interdisciplinary nature of these topics a dialog between simulation practitioners and computer technology developers will grow in importance. Several panelists, consisting of a mixture of simulation practitioners and computer scientists will describe their recent experiences in simulating systems on parallel computer configurations, highlighting efficiency comparisons and speculating on the general utility of such machines for simulation enterprises.

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Implementation of encryption algorithms on transport triggered architectures

Implementation of encryption algorithms on transport trigger...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： P. Hamalainen M. Hannikainen T. Hamalainen H. Corporaal J. Saarvinen Digital and Computer Systems Laboratory Tampere University of Technology Tampere Finland Tampereen yliopisto - Hervannan kampus Tampere Pirkanmaa FI DESICS IMEC Leuven Belgium

ISBN: (纸本)0780366859

The paper studies a configurable processor architecture, transport triggered architecture (TTA), for encryption algorithm implementations. The automatic TTA design space exploration is applied and configurations with good cost-performance ratio are found. It is shown that TTAs are at least equal to commercial processors in performance. According to earlier studies the performance level is also achieved at far lower cost. This encourages further development with tuned functionality.

关键词： Cryptography Computer architecture Registers Embedded system parallel processing Communication system security Hardware Central Processing Unit Multiprocessor interconnection networks Laboratories

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