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Instruction-Based High-Efficient Synchronization in a Many-Core Network-on-Chip Processor

Instruction-Based High-Efficient Synchronization in a Many-C...

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IEEE international symposium on Circuits and Systems

作者： Zhenqi Wei Peilin Liu Zhencheng Zeng Jiangwei Xu Rendong Ying School of Electronic Information and Electrical Engineering Shanghai Jiao Tong University Shanghai China

ISBN: (纸本)9781479934331

parallelized applications running on many-core Network-on-Chip (NoC) processors may consume a great part of execution time to synchronize threads mapped on multiple NoC nodes, if synchronization for NoC processors is not carefully designed. In this paper, we propose an instruction-based synchronization solution applied in a packet-switched many-core NoC processor with 2D mesh grid topology. Return links are added into the on-chip network to transmit acknowledgements of read requests, while a specific instruction SET is designed as instruction set extension to the original pipeline to perform atomic read-modify-write operations. To support various synchronization schemes, a hardware unit SYNC containing globally addressable registers as shared variables is adopted to handle synchronization requests from both local and remote NoC nodes. Additionally, a FIFO located in the SYNC unit can store these synchronization requests to poll on shared variables locally. Thus, network contention due to busy-wait synchronization algorithms is greatly reduced. Synchronization schemes including spinlock, barrier, FIFO spinlock and semaphore are implemented as inline assembly functions. Synthesis results under 55nm process suggest low area and power overhead of the hardware design. Performance of synchronization schemes are evaluated and are compared to results of conventional methods and prior works, showing the proposed solution is of higher efficiency.

关键词： NoC parallel programming Thread Synchronization Atomic Operation parallel programming network-on-chip atomic operation NOCT gene core network PROCESSOR signals instruction sets

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An efficient algorithm for large-scale matrix transposition

An efficient algorithm for large-scale matrix transposition

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international Conference on parallel Processing (ICPP)

作者： Jinwoo Suh V.K. Prasanna USC Information Sciences Institute Arlington VA USA Department of EE-Systems EEB-200C University of Southern California Los Angeles CA USA

Efficient transposition of large-scale matrices has been widely studied. These efforts have focused on reducing the number of I/O operations. However, in the state-of-the-art architectures, data transfer time and index computation time are also significant components of the overall time. In this paper, we propose an algorithm that considers all these costs and reduces the overall execution time. The reduction of the overall execution time is achieved by using two techniques: (1) writing the data onto disk in predefined patterns and (2) balancing the numbers of disk read and write operations. Even though our approach may increase the number of I/O operations for some cases it results in an overall reduction in the execution time. The index computation time, which is an expensive operation involving two divisions and a multiplication, is eliminated by partitioning the memory into two buffers. The expensive in-processor permutation is replaced by data collection operations. Our algorithm is analyzed using the well-known Linear Model and the parallel Disk Model. The experimental results on a Sun Enterprise and a DEC Alpha show that our algorithm reduces the execution time by about 50%, compared with the best known algorithms in the literature.

关键词： Large-scale systems Costs Art Computer architecture Writing Algorithm design and analysis Sun programming environments Positron emission tomography Contracts

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A Study of Single and Multi-device Synchronization Methods in Nvidia GPUs

A Study of Single and Multi-device Synchronization Methods i...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Lingqi Zhang Mohamed Wahib Haoyu Zhang Satoshi Matsuoka Tokyo Institute of Technology National Institute of Advanced Industrial Science and Technology miHoYo Inc RIKEN Center for Computational Science

ISBN: (数字)9781728168760

ISBN: (纸本)9781728168777

GPUs are playing an increasingly important role in general-purpose computing. Many algorithms require synchronizations at different levels of granularity in a single GPU. Additionally, the emergence of dense GPU nodes also calls for multi-GPU synchronization. Nvidia's latest CUDA provides a variety of synchronization methods. Until now, there is no full understanding of the characteristics of those synchronization methods. This work explores important undocumented features and provides an in-depth analysis of the performance considerations and pitfalls of the state-of-art synchronization methods for Nvidia GPUs. The provided analysis would be useful when making design choices for applications, libraries, and frameworks running on single and/or multi-GPU environments. We provide a case study of the commonly used reduction operator to illustrate how the knowledge gained in our analysis can be useful. We also describe our micro-benchmarks and measurement methods.

关键词： Synchronization Graphics processing units Kernel programming Instruction sets Throughput

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Proceedings. 2003 international symposium on System-on-Chip (IEEE Cat. No.03EX748)

Proceedings. 2003 International Symposium on System-on-Chip ...

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IEEE international symposium on System-on-Chip

The following topics are dealt with: ASIC; SOPC; dynamic instruction scheduling; VLIW-DISVLIW; SoC integration; programmable cores; logic development; software-defined radio; NoC; CMOS; electronic ballasts; fluorescent lamps; application mapping; network simulation; network-on-chip; code compression scheme; AMBA; multiprocessor system; CTL; matrix inverse; fixed-point representation; iterative methods; network processor; low power datapath; algebraic codebook search; system-on-chip; complexity analysis; MPEG-4 encoder; application specific algorithms; IP-methodology; compressed transport; C-based algorithm; reconfigurable processor architecture; XICU; interrupt control unit; DSP; interconnects; inductive crosstalk; capacitive crosstalk; noise cancellation; dynamic clamping; dynamic shielding; RLC buses; communication generator; arithmetic processing unit; reciprocal operations; routing algorithm; mappability estimate; processor-algorithm pair; multiple-objective backtrace; test generation constraints; IP integration; energy consumption; delay spread; FFT processor; wireless receivers; Ethernet; loopback BIST; RF front-ends; digital transceivers; RTOS modelling; multiprocessors; flip-flops; integrated circuits; switching regulators; static profiling; dynamic profiling; code compression; AVISPA; and reconfigurable accelerator.

关键词： Application specific integrated circuits Logic design Integrated circuit design Logic programming CMOS integrated circuits Multiprocessing Iterative methods Processor scheduling Reconfigurable architectures Digital signal processors Transceivers

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ResNet Can Be Pruned 60×: Introducing Network Purification and Unused Path Removal (P-RM) after Weight Pruning

ResNet Can Be Pruned 60×: Introducing Network Purification ...

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IEEE international symposium on Nanoscale architectures (NANOARCH)

作者： Xiaolong Ma Geng Yuan Sheng Lin Zhengang Li Hao Sun Yanzhi Wang Department of Electrical and Computer Engineering Northeastern University Department of Civil and Environmental Engineering Northeastern University

ISBN: (数字)9781728155203

ISBN: (纸本)9781728155210

The state-of-art DNN structures involve high computation and great demand for memory storage which pose intensive challenge on DNN framework resources. To mitigate the challenges, weight pruning techniques has been studied. However, high accuracy solution for extreme structured pruning that combines different types of structured sparsity still waiting for unraveling due to the extremely reduced weights in DNN networks. In this paper, we propose a DNN framework which combines two different types of structured weight pruning (filter and column prune) by incorporating alternating direction method of multipliers (ADMM) algorithm for better prune performance. We are the first to find nonoptimality of ADMM process and unused weights in a structured pruned model, and further design an optimization framework which contains the first proposed Network Purification and Unused Path Removal algorithms which are dedicated to post-processing an structured pruned model after ADMM steps. Some high lights shows we achieve 232× compression on LeNet-5, 60× compression on ResNet-18 CIFAR-10 and over 5× compression on AlexNet. We share our models at anonymous link http://***/2VJ5ktv.

关键词： Convex functions Optimization Computational modeling Nanoscale devices Acceleration Linear programming Standards

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parallel Retrograde Analysis on Different Architecture 01

Parallel Retrograde Analysis on Different Architecture

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Proceedings of the 10th IEEE international symposium on High Performance Distributed Computing

作者： Ren Wu

Abstract: Retrograde analysis is an efficient exhaustive search method. It is a powerful tool that can be used in solving problems where end states have known values but starting states do not. It has been widely used to solve mathematically-precise games such as chess endgames, and is potentially usable in energy-minimization problems. With increasing computing power, both in speed and storage capacity, retrograde analysis will become more and more useful. This paper looks at successful applications to games, the challenges ahead, and the modifications that are required to utilize distributed hardware. The power and the usefulness of retrograde analysis are still limited by the computing resources one has access to. Today, the best sequential retrograde algorithms are capable of solving problems with about 10 9 states in a few hours on a standard personal computer. Bigger problems need more powerful computers, or take much longer to solve, or are simply out of reach of today's technologies. Introducing parallelism to retrograde analysis is a natural way to attack the bigger problems. There are today three main architectures available for doing parallel retrograde analysis: namely Symmetric Multiprocessor systems, High-speed network based distributed systems, and Internet based distributed systems. In this paper, we discuss some of the key issues in doing parallel retrograde analysis on these different architectures. Technical challenges are addressed in detail, as well as some examples and proposals. These examples and proposals are drawn from various board games, but the ideas can be applied to other problem domains.

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A Hartree-Fock Application Using UPC++ and the New DArray Library

A Hartree-Fock Application Using UPC++ and the New DArray Li...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： David Ozog Amir Kamil Yili Zheng Paul Hargrove Jeff R. Hammond Allen Malony Wibe de Jong Kathy Yelick University of Oregon Eugene Oregon USA Lawrence Berkeley National Laboratory Berkeley California USA Intel Corporation Portland Oregon USA Lawrence Berkeley Nat. Lab. Berkeley CA US

ISBN: (纸本)9781509021413

The Hartree-Fock (HF) method is the fundamental first step for incorporating quantum mechanics into many-electron simulations of atoms and molecules, and it is an important component of computational chemistry toolkits like NWChem. The GTFock code is an HF implementation that, while it does not have all the features in NWChem, represents crucial algorithmic advances that reduce communication and improve load balance by doing an up-front static partitioning of tasks, followed by work stealing whenever necessary. To enable innovations in algorithms and exploit next generation exascale systems, it is crucial to support quantum chemistry codes using expressive and convenient programming models and runtime systems that are also efficient and scalable. This paper presents an HF implementation similar to GTFock using UPC++, a partitioned global address space model that includes flexible communication, asynchronous remote computation, and a powerful multidimensional array library. UPC++ offers runtime features that are useful for HF such as active messages, a rich calculus for array operations, hardware-supported fetch-and-add, and functions for ensuring asynchronous runtime progress. We present a new distributed array abstraction, DArray, that is convenient for the kinds of random-access array updates and linear algebra operations on block-distributed arrays with irregular data ownership. We analyze the performance of atomic fetch-and-add operations (relevant for load balancing) and runtime attentiveness, then compare various techniques and optimizations for each. Our optimized implementation of HF using UPC++ and the DArrays library shows up to 20% improvement over GTFock with Global Arrays at scales up to 24,000 cores.

关键词： Arrays Libraries Electronics packaging Hafnium Computational modeling programming

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Coupling of ANNN with GA for effective optimization of dimensions of rectangular patch antenna on thick substrate microstrip patch antenna on thick substrate

Coupling of ANNN with GA for effective optimization of dimen...

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international symposium on Antennas, Propagation and EM Theory (ISAPE)

作者： D.C. Panda S.S. Pattnaik B. Khuntia D.K. Neog S. Devi NERIST Nirjuli Arunachal Pradesh India Dhemaji College Assam India

A novel method of optimization by coupling the genetic algorithm (GA) and artificial neural network (ANN) is presented in this paper. A trained artificial neural network is taken as objective function in GA for optimization. By utilizing this technique the optimized dimensions of patch antenna on thick substrate has been calculated. It is seen that the results obtained by this method are closer to experimental value compared to earlier results obtained by curve fitting method. To validate this, the results are compared with experimental values for five fabricated antenna. The results are in very good agreement with experimental findings.

关键词： Microstrip antennas Patch antennas Artificial neural networks Genetic algorithms Resonant frequency parallel architectures Genetic mutations Biological cells Educational institutions Optimization methods

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A vector based fast block motion estimation algorithm for implementation on SIMD architectures

A vector based fast block motion estimation algorithm for im...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： C. Duanmu M.O. Ahmad M.N.S. Swamy A. Shatnawi Department of Electrical & Computer Engineering Center for Signal Processing and Communications Concordia University Montreal QUE Canada

In this paper, a fast block motion estimation algorithm that not only accelerates the process of the motion estimation but also maintains the same accuracy as that of the full search algorithm is proposed. In modern CPUs, the single instruction multiple data (SIMD) technique is commonly used to provide an execution speedup of up to eight fold. The proposed algorithm satisfies the requirements of (i) the easy computation of the lower bounds of the block matching error, and (ii) their storage in a contiguous memory space for its SIMD implementation. Simulation results show that the proposed algorithm is more than 40 times faster than the full search algorithm while keeping the accuracy of the latter.

关键词： Motion estimation Signal processing algorithms Computer architecture Acceleration Modems Video coding Maintenance engineering Computational modeling MPEG 4 Standard parallel processing

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parallel extended-Born analysis of electromagnetic scattering from 3-dimensional sub-rough surface targets

Parallel extended-Born analysis of electromagnetic scatterin...

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Antennas and Propagation Society international symposium

作者： Tiejun Yu L. Carin Cadence Design Systems Inc. San Jose CA USA Department of ECE Duke University Durham NC USA

The real 3-dimensional rough surface (RS) half space is treated as a perfect half-space with a special target which leads to a huge problem size if the integral equation (IE) based method of moments (MoM) is used, so a parallel algorithm is applied to speedup the EM scattering calculation from the RS. The message-passing interface (MPI) is the most widely used new standard for parallel calculation. It is not a new programming language, rather it is a library of subprograms that can be called from C++ and Fortran programs. In the paper, a powerful cluster with 33-CPU units connected by MPI network technique provides a good chance to investigate the real 3D RS half space EM scattering. Instead of rigorous MoM, a more efficient algorithm named extended-Born (E-Born) is used to model this 3D RS scattering problem. As E-Born is a very natural parallel algorithm, the complete parallel E-born code is almost P times fast as a series E-born code, where P is the CPU number in the cluster. When N is the problem size which is usually very large for real 3D-RS scattering, the LU-decomposition (LUD) solution of MoM is of the order of N/sup 3/ complexity, while a series E-Born solution is of the order of 27N, and the parallel E-Born solution is of the order of 27N/P. With such a computational complexity of 27N/P, a problem with size N >10/sup 5/ is no longer a prohibitive task. The accuracy and efficiency of the parallel E-Born method are validated by the MoM results.

关键词： Electromagnetic analysis Electromagnetic scattering Rough surfaces Surface roughness Surface treatment parallel algorithms Integral equations Moment methods Computer languages Libraries

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